Mobility Of Metal-oxide-semiconductor Field-effect Transistors Research Articles

Comparison of the Performance-Degrading Near-Interface Traps in Commercial SiC MOSFETs

This paper presents a comparison of the density of performance-degrading near-interface traps (NITs) in the most commonly available 1200 V commercial N-channel SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). A recently developed integrated-charge technique was used to measure the density of NITs with energy levels aligned to the conduction band, which degrade MOSFET’s performance by capturing and releasing electrons from the channel biased in the strong-inversion condition. Trench MOSFETs of one manufacturer have lower densities of these NITs in comparison to MOSFETs with the planar gate structure, corresponding to observed higher channel-carrier mobility in trench MOSFETs. Different response-time distributions were also observed, corresponding to different spatial location of the measured NITs.

Improvement of channel-carrier mobility in 4H-SiC MOSFETs correlated with passivation of very fast interface traps using sodium enhanced oxidation

Very fast interface traps have recently been suggested to be the main cause behind the rather poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors (MOSFETs). Using capacitance voltage analysis and conductance spectroscopy on metal oxide semiconductor capacitors, at cryogenic temperatures, we find that these fast traps are absent in oxides made by sodium enhanced oxidation, and high inversion channel-carrier mobility in MOSFETs made by sodium enhanced oxidation is observed.

Electrically Active Defects in SiC Power MOSFETs

The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect.

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis.

The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field () on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be and , respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of in controlling the value of channel mobility in 4H-SiC MOSFETs.

Effective channel mobility in phosphorus-treated 4H-SiC (0001) metal-oxide-semiconductor field-effect transistors with various p-body doping concentrations

Phosphorus treatment, which can substantially reduce the interface state density (D it), was used to investigate the impact of D it on effective channel mobility (μ eff) of 4H-SiC (0001) metal-oxide-semiconductor field-effect transistors (MOSFETs). A high μ eff of 126 cm2 V−1 s−1, which exceeds the reported phonon-limited mobility of 83 cm2 V−1 s−1 determined from Hall mobility of nitridation-treated MOSFETs, at a high effective normal field of 0.57 MV cm−1 was obtained in MOSFETs fabricated on a high-purity semi-insulating 4H-SiC substrate at room temperature. This high mobility may be caused by the difference of the density of electrons trapped at the interface states.

Impacts of Al2O3/SiO2 Interface Dipole Layer Formation on the Electrical Characteristics of 4H-SiC MOSFET

In this letter, we demonstrated an approach to introduce a positive shift in transfer curves of lateral metal-oxide-semiconductor field-effect transistors (MOSFETs) on 4H-SiC (0001), without deterioration of channel conductance. With an additional Al₂O₃ thin film on thermally grown SiO₂ after the nitridation process, a dipole layer was formed at the Al₂O₃/SiO₂ interface, which induced the positive shift of flat-band voltage. The field-effect mobility of MOSFET was not changed after the Al₂O₃ fabrication process, which means that the quality of the nitrogen-passivated SiO₂/SiC interface was not damaged by this process.

Comparative Study of Hall Effect Mobility in Inversion Layer of 4H-SiC MOSFETs With Nitrided and Phosphorus-Doped Gate Oxides

In this study, the inversion layer mobility characteristics in Si-face 4H silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with nitrided and phosphorus-doped gate oxides were compared using Hall effect measurements. The inversion layer mobility was evaluated by applying a body bias and changing the temperature. The carrier scattering properties were determined for elevated temperatures (i.e., 473 K), at which point the impact of Coulomb scattering decreases and that of phonon scattering increases. The phonon-limited mobility of these MOSFETs was almost the same when plotted as a function of the effective normal electric field in the inversion layer, possibly representing the nature of the thermally grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiC interface. On the basis of this finding, the effect of phonon scattering was separated from the inversion layer mobility. The MOSFETs exhibited a remarkable difference in Coulomb scattering: the MOSFETs with phosphorus-doped gate oxide exhibited a more rapid increase in Coulomb-limited mobility with increasing surface carrier density than did the MOSFETs with nitride gate oxide. This resulted from the effective suppression of Coulomb scattering in the inversion layer, which is one of the reasons why phosphorus-doped gate oxide achieves higher inversion layer mobility than nitrided gate oxide. These results show that the inversion layer mobility of SiC MOSFETs can be modeled using a conventional framework of phonon, Coulomb, and surface roughness scattering. Therefore, the suppression of Coulomb scattering is key to further improving the inversion layer mobility of SiC MOSFETs.

Channel Properties of Ga₂O₃-on-SiC MOSFETs

We report the characterization of the channel mobility properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) on the heterogeneous $\beta $ -Ga2O3-on-SiC (GaOSiC) substrate fabricated by an ion-cutting process. The mobility of GaOSiC MOSFETs is significantly improved as the postannealing temperature of Ga2O3 channel increases from 900 °C to 1200 °C. The GaOSiC transistor annealed at 1200 °C exhibits mobility consistent with the $\beta $ -Ga2O3 donor wafer, which suggests that the defects in Ga2O3 channel induced by the H+ implantation for the ion-cutting step can be eliminated by the high-temperature annealing. As the ambient temperature ( ${T} _{{\mathrm {amb}}}$ ) increases from 0 °C to 150 °C, the mobility within the accumulation regime of GaOSiC MOSFETs decreases with the temperature following a ${T}_{{\mathrm {amb}}}^{-1}$ law, which is limited by the phonon scattering. The results of this work will be critically important for designing the transport properties of the GaOSiC channel, significantly advancing the development of Ga2O3 power devices on high thermal conductivity substrate.

Influence of Non-Uniform Interface Defect Clustering on Field-Effect Mobility in SiC MOSFETs Investigated by Local Deep Level Transient Spectroscopy and Device Simulation

It has recently been shown that interface defect density (Dit) at SiO2/SiC interfaces can have non-uniform clustered distribution through the measurement by local deep level transient spectroscopy (local DLTS). Here we investigate the influence of the non-uniform Dit clustering on the field-effect mobility in SiC metal-oxide-semiconductor field effect transistors (MOSFETs) by device simulation. We develop a three dimensional numerical model of a SiC MOSFET, which can incorporate actual Dit distributions measured by local DLTS. Our main result is that the impact of the non-uniform Dit clustering on field-effect mobility is negligible for a SiC MOSFET with high Dit formed by dry thermal oxidation but it becomes significant for that with lower Dit by post-oxidation annealing. The result indicates that channel mobility can be further improved by making Dit distribution uniform as well as reducing Dit.

Insight into Channel Conduction Mechanisms of 4H-SiC(0001) MOSFET Based on Temperature-Dependent Hall Effect Measurement

Temperature-dependent Hall effect measurements were conducted to investigate the channel conduction mechanisms of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). This method allows us to discriminate the impact of the density of mobile (free) carriers in the inversion channels and their net mobility on the performance of SiC MOSFETs. It was found that, while the free carrier ratio of SiC MOSFETs with conventional gate oxides formed by dry oxidation is below 4% at 300 K, increasing the free carrier ratio due to thermal excitation of trapped electrons from SiO2/SiC interfaces leads to an unusual improvement in the field-effect mobility of SiC MOSFETs at elevated temperatures. Specifically, a significant increase in free carrier density surpasses the mobility degradation caused by phonon scattering for thermally grown SiO2/SiC interfaces. It was also found that, although nitrogen incorporation in SiO2/SiC interfaces increases the free carrier ratio typically up to around 30%, introduction of an additional scattering factor associated with interface nitridation compensates for the moderate amount of thermally generated mobile carriers at high temperatures, indicating a fundamental drawback of nitridation of SiO2/SiC interfaces. On the basis of these findings, we discuss the channel conduction mechanisms of SiC MOSFETs.

High-mobility SiC MOSFET with low density of interface traps using high pressure microwave plasma oxidation**Project supported in part by the National Key Research and Development Program of China (Grant No. 2016YFB0100601), the National Natural Science Foundation of China (Grant Nos. 61674169 and 61974159), and the Support from a Grant-In-Aid from the Youth Innovation Promotion Association of the Chinese Academy of

The microwave plasma oxidation under the relatively high pressure (6 kPa) region is introduced into the fabrication process of SiO2/4H-SiC stack. By controlling the oxidation pressure, species, and temperature, the record low density of interface traps (∼ 4 × 1010 cm−2⋅eV−1@Ec − 0.2 eV) is demonstrated on SiO2/SiC stack formed by microwave plasma oxidation. And high quality SiO2 with very flat interface (0.27-nm root-mean-square roughness) is obtained. High performance SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) with peak field effect mobility of 44 cm−2 ⋅eV−1 is realized without additional treatment. These results show the potential of a high-pressure plasma oxidation step for improving the channel mobility in SiC MOSFETs.

Insight into enhanced field-effect mobility of 4H-SiC MOSFET with Ba incorporation studied by Hall effect measurements

Improved performance in 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) by incorporating Ba into insulator/SiC interfaces was investigated by using a combination of the Hall effect and split capacitance-voltage measurements. It was found that a moderate annealing temperature causes negligible metal-enhanced oxidation, which is rather beneficial for increments in field-effect mobility (μFE) of the FETs together with suppressed surface roughness of the gate oxides. The combined method revealed that, while severe μFE degradation in SiC-MOSFETs is caused by a reduction of effective mobile carriers due to carrier trapping at the SiO2/SiC interfaces, Ba incorporation into the interface significantly increases mobile carrier density with greater impact than the widely-used nitrided interfaces.

Effects of high-temperature diluted-H2 annealing on effective mobility of SiC MOSFETs estimated by split capacitance–voltage technique

The effects of post-oxidation annealing (POA) in diluted-H2 ambient on 4H- and 6H-SiC/SiO2 interfaces were investigated. Effective mobility (μeff) was extracted from lateral metal–oxide–semiconductor field-effect transistors (MOSFETs) by the split capacitance–voltage (C–V) technique to determine the surface charge density and a calibration technique using two MOSFETs with different gate lengths to minimize the contribution of parasitic components. POA at 1150 °C in diluted-H2 ambient resulted in an enhancement of μeff, compared with that in N2 ambient. It was indicated that the effects of POA in diluted-H2 ambient should be attributed to the reduction in the density of near-interface traps in oxide, which disturb the electron transportation in the inversion channel, from the measurement temperature dependence of μeff for 6H-SiC MOSFETs as well as from the C–V curves of MOS capacitors fabricated on n-type 4H-SiC.

(Invited) Interface Defects in C-face 4H-SiC MOSFETs: An Electrically-Detected-Magnetic-Resonance Study

Using electrically-detected-magnetic-resonance spectroscopy and a device simulation, we studied dominant interface defects, named “C-face defects,” in C-face 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The C-face defects act as hole traps via their donor levels, when they are not passivated by hydrogen atoms. The densities of unpassivated C-face defects were estimated to be from 4x1012 cm-2 to 13x1012 cm-2 in various C-face MOSFETs, which correlated with negative threshold-voltage (V th) shifts. We explained influences of the C-face defects on the V th instability and the channel mobility of C-face MOSFETs.

High-Mobility SiC MOSFETs with Alkaline Earth Interface Passivation

Alkaline earth elements Sr and Ba provide SiO2/SiC interface conditions suitable for obtaining high channel mobility metal-oxide-semiconductor field-effect-transistors (MOSFETs) on the Si-face (0001) of 4H-SiC, without the standard nitric oxide (NO) anneal. The alkaline earth elements Sr and Ba located at/near the SiO2/SiC interface result in field-effect mobility (μFE) values as high as 65 and 110 cm2/V.s, respectively, on 5×1015 cm-3 Al-doped p-type SiC. As the SiC doping increases, peak mobility decreases as expected, but the peak mobility remains higher for Ba interface layer (Ba IL) devices compared to NO annealed devices. The Ba IL MOSFET field-effect mobility decreases as the temperature is increased to 150 °C, as expected when mobility is phonon-scattering-limited, not interface-trap-limited. This is in agreement with measurements of the interface state density (DIT) using the high-low C-V technique, indicating that the Ba IL results in lower DIT than that of samples with nitric oxide passivation. Vertical power MOSFET (DMOSFET) devices (1200V, 15A) fabricated with the Ba IL have a 15% lower on-resistance compared to devices with NO passivation. The DMOSFET devices with a Ba IL maintain a stable threshold voltage under NBTI stress conditions of-15V gate bias stress, at 150 °C for 100hrs, indicating no mobile ions. Secondary-ion mass-spectrometry (SIMS) analysis confirms that the Sr and Ba remain predominantly at the SiO2/SiC interface, even after high temperature oxide annealing, consistent with the observed high channel mobility after these anneals. The alkaline earth elements result in enhanced SiC oxidation rate, and the resulting gate oxide breakdown strength is slightly reduced compared to NO annealed thermal oxides on SiC.

Effects of high-temperature diluted-H2 annealing on effective mobility of 4H-SiC MOSFETs with thermally-grown SiO2

The impact of post-oxidation annealing (POA) in diluted-H2 ambient on a 4H-SiC/SiO2 interface was investigated with a cold wall furnace. Effective mobility (μeff) was extracted from lateral metal–oxide–semiconductor field-effect transistors (MOSFETs) by applying the split capacitance–voltage (C–V) technique to the determination of charge density and a calibration technique using two MOSFETs with different gate lengths to minimize the contribution of parasitic components. POA at 1150 °C in diluted-H2 ambient resulted in an enhancement of μeff compared with that for POA in N2 ambient. It was indicated that the effects of POA in diluted H2 should be attributed to the reduction in the density of near interface traps, which disturb the electron transportation in the inversion channel, from the measurement temperature dependence of μeff as well as from the C–V curves of MOS capacitors fabricated on n-type SiC.

Properties of ultrathin-body condensation Ge-on-insulator films thinned by additional thermal oxidation

In this paper, we report the properties of ultrathin-body (UTB) Ge-on-insulator (GOI) films thinned by additional thermal oxidation after Ge condensation and p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) on the thinned GOI layers. By using the present process, we have demonstrated the thinning of GOI layers to a thickness of around 6 nm and the operation of UTB GOI pMOSFETs with a GOI thickness of 9.7 nm. We have characterized the physical and electrical properties of the GOI layers formed by Ge condensation and those of the thinned GOI layers fabricated by additional thermal oxidation. The additional oxidation resulted in an increase in hole concentration in the GOI layers and a change in strain in the GOI layers from compressive to tensile, attributed by defect generations during the thinning process. The higher hole concentration in the thinner GOI layer can degrade the effective mobility in GOI MOSFETs.

Improved Channel Mobility in 4H-SiC MOSFETs by Boron Passivation

We propose another process for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high channel mobility. The B atoms were introduced into a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /4H-SiC interface by thermal annealing with a BN planar diffusion source. The interface state density near the conduction band edge of 4H-SiC was effectively reduced by the B diffusion and the fabricated 4H-SiC MOSFETs showed a peak field-effect mobility of 102 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs. The obtained high channel mobility cannot be explained by counter doping because B atoms act as acceptors in 4H-SiC. We suggest that the interfacial structural change of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> may be responsible for the reduced trap density and enhanced channel mobility.

Performance Analysis of Cntfet and Mosfet Focusing Channel Length, Carrier Mobility and Ballistic Conduction in High Speed Switching

Enhancement of switching in nanoelectronics, Carbon Nano Tube (CNT) could be utilized in nanoscaled Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In this revi ew, we present an in depth discussion of performances Carbon Nanotube Field Effect Transistor (CNTFET) and its significance in nanoelectronic circuitry in comparison with Metal Oxide Semiconductor Field Effect Transistor (MOSFET). At first, we have discuss ed the structural unit of Carbon Nanotube and characteristic electrical behaviors beteween CNTFET and MOSFET. Short channel effect and effects of scattering and electric field on mobility of CNTFET and MOSFET have also been discussed. Besides, the nature o f ballistic transport and profound impact of gate capacitance along with dielectric constant on transconductance have also have been overviewed. Electron ballistic transport would be the key in short channel regime for high speed switching devices. Finally, a comparative study on the characteristics of contact resistance over switching capacity between CNTFET and MOSFET has been addressed.

Mobility characterization of Ge-on-insulator metal-oxide-semiconductor field-effect transistors with striped Ge channels fabricated by lateral liquid-phase epitaxy

High-mobility metal-oxide-semiconductor field-effect transistors (MOSFETs) consisting of stripe-shaped local germanium-on-insulator (GOI) structures were fabricated by lateral liquid-phase epitaxy (LLPE). The effective hole mobility of back-gate LLPE-grown GOI MOSFETs was accurately and reliably evaluated with a split capacitance-voltage (C-V) method. The superior effective hole mobility of the GOI devices throughout a wide range of accumulated carrier densities over that for a reference silicon-on-insulator device was demonstrated. A very high peak hole mobility of 511 cm2/Vs and an on/off current ratio of 106, together with phonon scattering limited carrier mobility at high temperatures, indicated not only the excellent crystalline quality of LLPE-grown GOI but also surprisingly good interface quality between Ge and the buried oxide.