Mobile Industry Processor Interface Research Articles

Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface

A backdoor attack is a type of attack method that induces deep neural network (DNN) misclassification. The adversary who aims to trigger the backdoor attack inputs the image with a specific pattern (the adversarial mark) into the DNN model (backdoor model). In general, the adversary mark is created on the physical object input to an image by capturing a photo. With this conventional method, the success of the backdoor attack is not stable because the size and position change depending on the shooting environment. So far, we have proposed a method of creating an adversarial mark for triggering backdoor attacks by means of a fault injection attack on the mobile industry processor interface (MIPI), which is the image sensor interface. We propose the image tampering model, with which the adversarial mark can be generated in the actual fault injection to create the adversarial mark pattern. Then, the backdoor model was trained with poison data images, which the proposed simulation model created. We conducted a backdoor attack experiment using a backdoor model trained on a dataset containing 5% poison data. The clean data accuracy in normal operation was 91%; nevertheless, the attack success rate with fault injection was 83%.

Preview the Products on Display at Display Week 2023

Preview the Products on Display at Display Week 2023

A 1.8-2.7 GHz Triple-Band Low Noise Amplifier with 31.5 dB Dynamic Range of Power Gain and Adaptive Power Consumption for LTE Application.

This paper presents a multi-gain radio frequency (RF) front-end low noise amplifier (LNA) utilizing a multi-core based on the source degeneration topology. The LNA can cover a wide range of input and output frequency matching by using a receiver (RX) switch at the input and a capacitor bank at the output of the LNA. In the proposed architecture here, to avoid the saturation of RX chain, 12 gain steps including positive, 0 dB, and negative power gains are controlled by a mobile industry processor interface (MIPI). The multi-core architecture offers the ability to control the power consumption over different gain steps. In order to avoid the phase discontinuity, the negative gain steps are provided using an active amplification and T-type attenuation path that keeps the phase discontinuity below ±5 degrees between two adjacent power gain steps. Using the multi-core structure, the power consumption is optimized in different power gains. The structure is enhanced with the adaptive variable cores and reactance parameters to maintain different power consumption for different gain steps and remain the output matching in an acceptable operating range. Furthermore, auxiliary linearization circuitries are added to improve the input third intercept point (IIP3) performance of the LNA. The chip is fabricated in 65 nm complementary metal-oxide semiconductor (CMOS) silicon on insulator (SOI) process and the die area is 0.308 mm2. The proposed architecture achieves the IIP3 performance of −10.2 dBm and 8.6 dBm in the highest and lowest power gains, which are 20.5 dB and −11 dB, respectively. It offers the noise figure (NF) performance of 1.15 dB in the highest power gain while it reaches 14 dB when the power gain is −11 dB. The LNA consumes 16.8 mA and 1.33 mA current from a 1 V power supply that is provided by an on-chip low-dropout (LDO) when it operates at the highest and lowest gains, respectively.

A 92-μW/Gbps Self-Biased SLVS Receiver for MIPI D-PHY Applications

This brief introduces a self-biased Scalable Low-Voltage Signaling (SLVS) receiver circuit in order to minimize the power dissipation on D-PHY layer of the Mobile Industry Processor Interface (MIPI). This design does not require any static bias circuitry. It can also support an input common-mode voltage of the receiver as low as 50 mV. This allows D-PHY transmitter to use lower common-mode voltage further reducing the power dissipation of the transceiver pair of D-PHY layer. It is fabricated in a 180-nm CMOS process. The test results show that it operates up to 2 Gbps at 1.2 V power supply in High Speed-mode (HS-mode) of MIPI D-PHY standard. The power efficiency is 92 $\mu \text{W}$ /Gbps or 77 $\mu \text{A}$ /Gbps.

A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor.

A 3.0 Gsymbol/s/lane receiver is proposed herein to acquire near-grounded high-speed signals for the mobile industry processor interface (MIPI) C-PHY version 1.1 specification used for CMOS image sensor interfaces. Adaptive level-dependent equalization is also proposed to improve the signal integrity of the high-speed receivers receiving three-level signals. The proposed adaptive level-dependent equalizer (ALDE) is optimized by adjusting the duty cycle ratio of the clock recovered from the received data to 50%. A pre-determined data pattern transmitted from a MIPI C-PHY transmitter is established to perform the adaptive level-dependent equalization. The proposed MIPI C-PHY receiver with three data lanes is implemented using a 65 nm CMOS process with a 1.2 V supply voltage. The power consumption and area of each lane are 4.9 mW/Gsymbol/s/lane and 0.097 mm2, respectively. The proposed ALDE improves the peak-to-peak time jitter of 12 ps and 34 ps, respectively, for the received data and the recovered clock at a symbol rate of 3 Gsymbol/s/lane. Additionally, the duty cycle ratio of the recovered clock is improved from 42.8% to 48.3%.

Preview the Products on Display at Display Week 2021

Preview the Products on Display at Display Week 2021

A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization

A 3.0 GSymbol/s/lane transceiver bridge chip, which fully supports the mobile industry processor interface (MIPI) C-PHY version 1.1 specification, is proposed for field-programmable gate array (FPGA)-based pattern generators and frame grabbers. In transmit mode, it converts parallel low-voltage complementary metal oxide semiconductor (CMOS) signals into high-speed three-level signals when performing serialization. In addition, deserialization including clock recovery from the received data is performed for its receive mode operation. A pre-emphasis transmitter and an elastic receiver that perform equalization according to the signal level are proposed to improve the signal integrity of high-speed three-level signals. The proposed MIPI C-PHY transceiver bridge chip is implemented using a 65 nm CMOS process with 1.2 V supply voltage. The area of each lane is 0.103 mm2 and the power consumption in high-speed transmit and receive modes is 2.96 mW/Gbps/lane and 5.62 mW/Gbps/lane, respectively. The measured peak-to-peak time jitter of the proposed high-speed transmitter, receiver, and clock recovery are 0.27 UI, 0.35 UI, and 90 ps, respectively, at a data rate of 3 GSymbol/s/lane.

A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface

A 20-Gbps receiver bridge chip featuring auto-skew calibration and continuous-time linear equalization is proposed to support the mobile industry processor interface D-PHY version 2.0 specification with four data lanes and one clock lane. The proposed receiver bridge chip performs byte synchronization and 1-to-8 deserialization for converting high-speed scalable low-voltage signals into low-speed low-voltage complementary metal-oxide semiconductor signals. The proposed auto-skew calibration has a simple architecture and is insensitive to dynamic noise owing to the use of the multiple bits supplied from the deserializer as a result of the phase detector for the skew calibration. It is performed via a four-step sequential process to use the minimum time delay. The proposed receiver bridge chip is implemented using a 0.11 $\mu \text{m}$ CMOS process with a 1.2 V supply. The measured peak-to-peak time jitter of the signal recovered using the proposed receiver is 50 ps at a data rate of 5.0 Gbps/lane on a printed circuit board FR-4 10 inch channel. The proposed skew calibration reduces the time skew among the four data lanes and one clock lane to less than 10 ps.

Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications

This brief presents a fully adaptive high-speed serial interface designed in 28-nm planar CMOS technology for future mobile industry processor interface (MIPI)-compliant automotive microcontrollers operating at 12 Gb/s over long-reach channels. The transmitter has a voltage-mode driver and operates at full rate featuring an 8-tap feed-forward equalizer with tap programmability of 1/16. The transmitter’s output impedance tuning is performed through activation of different driver replicas. The half-rate receiver features an analog front-end which comprises a variable-gain amplifier and a continuous-time linear equalizer. The subsequent decision-feedback equalizer (DFE) has three programmable taps, the first of which is loop-unrolled to relax timing constraints. Another amplifier is embedded in the DFE’s summing node. We employ transistor-level simulations to assess the capability of the interface to optimally adapt to realistic channels: the DFE taps and the data sampling phase are automatically adapted by means of a behavioural implementation of an least mean squares algorithm based on information gathered through error sampling. Such an interface was simulated on channels representing likely MIPI A-PHY to-be-defined specifications featuring up to 33 dB loss at 6 GHz.

A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2

A 2.5-Gbps/lane receiver bridge chip, which fully supports the protocol of the D-PHY version 1.2 for the mobile industry processor interface (MIPI) camera serial interface (CSI)-2, is proposed for a field-programmable gate array (FPGA)-based frame grabber. The proposed receiver bridge chip converts four-lane high-speed data of scalable low-voltage signaling (SLVS) of the MIPI CSI-2 into 32 low-speed data of low-voltage CMOS (LVCMOS) signaling for a parallel interface with a FPGA chip. In order to achieve this, each data lane of the proposed receiver bridge chip has a 1-to-8 deserializer including a byte synchronizer. Furthermore, an asynchronous delay line per lane compensates the time skew among the five lanes, including a clock lane. A common-gate level shifter (CGLS) with a continuous-time linear equalizer (CTLE) is proposed to improve the voltage fain and bandwidth of the high-speed receiver. The proposed receiver bridge chip is implemented using a 0.11 μm CMOS process with a 1.2 V supply. The area and power consumption of the proposed receiver bridge chip are 5.29 mm2 and 7.2 me/Gbps/lane, respectively. The proposed CTLE of the high-speed receiver achieves the improved peak-to-peak time jitter of 0.3UI at a data rate of 3.0 Gbps/lane. The FPGA-based frame grabber processes the image or video data supplied by a camera sensor with the MIPI CSI-2 by using the proposed receiver bridge chip.

Ultra-wide-angle Wireless Endoscope with a Backend-camera-controller Architecture

Abstract This paper presents a wireless endoscope with an ultra-wide FOV (Field of View) of 130° and HD resolution (1280×720 pixels). The proposed endoscope consists of a camera head, cable, camera controller, and wireless handle. The lens module with a 150° degrees AOV (Angle of View) is achieved using the plastic injection-molding process to reduce manufacturing costs. A serial CMOS image sensor using the MIPI (Mobile Industry Processor Interface) CSI-2 (Camera Serial Interface-2) interface physically separates the camera processor from the camera head. The camera head and the cable have a compact structure due to the BCC (Backend-Camera-Controller) architecture. The size of the camera head and the camera controller is 8×8×26 mm and 7×55 mm, respectively. The wireless handle supports a UWB (Ultra-Wide-Band) or a Wi-Fi communication to transmit video data. The UWB link supports a maximum data transfer rate of ~37 Mbps to transmit video data with a resolution of 1280×720 pixels at a frame rate of 30 fps in the MJPEG (Motion JPEG) format. Although the Wi-Fi link provides a lower data transfer rate (~8 Mbps Max.), it has the advantage of flexible interoperability with various mobile devices. The latency of the UWB link is measured to be ~0.1 sec. The Wi-Fi link has a larger latency (~0.5 sec) due to its lower data transfer rate. The proposed endoscope demonstrates the feasibility of a high-performance yet low-cost wireless endoscope using the BCC architecture. To the best of the author’s knowledge, the proposed endoscope has the largest FOV among all presently existing wireless endoscopes.

Design on LCD Pattern Generation System Based on Mobile Industry Processor Interface

Design on LCD Pattern Generation System Based on Mobile Industry Processor Interface

The Analysis of the Transmission Signal Measured MIPI D-PHY

Analysis the characteristics of the measured transmission signal of Mobile Industry Processor Interface (MIPI) Display Serial Interface Physical Layer (D-PHY) interface based on a project platform. Firstly, introduces the transmission characteristics and mutual conversion process of physical layer about high-speed and low power mode, and by the transmission signal measured a platform of high-speed mode, present the D-PHY transmission signal each test items and test point selection, make the phone run smoothly and screen display normally, this test analysis certain practicability and expansibility.

A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler

A noncontact and housing-less thin–thick connecting method was developed for mobile industry processor interface (MIPI) applications. This paper describes the world's first 0.15-mm-thick connector using a vertical directional coupler (VDC) which enables simultaneous two-link communication with one coupler without fatal performance degradation. We have analyzed the conditions for isolating two links in a coupler, and the design method is discussed. A fully balanced pulse transmitter implemented in 90-nm CMOS technology significantly suppressed electromagnetic interference (EMI), which agrees well with MIPI requirements. An experimental liquid crystal display interface system reached a maximum data rate of 2.3 Gb/s/link at a bit error rate of less than <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$10^{-12}$</tex> </formula> and a power consumption of 1.47 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$~$</tex></formula> pJ/b. The timing margin of single link was 320 ps ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$=$</tex></formula> 64% U.I.) and of two links was 305 ps ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$=$</tex> </formula> 61% U.I.) at 2.0 Gb/s.

Design of High-Order Switches for Multimode Applications on a Silicon-on-Insulator Technology

A silicon-on-insulator (SOI) CMOS technology on high-resistivity silicon substrates is presented for the design of high-power switches for cellular and wireless local area network handset applications. A design methodology is introduced to design high-order switches for optimal insertion loss and isolation performance. Sources of nonlinearities in SOI switches are discussed. To the best of our knowledge, this work is the first demonstration of high-power switches on a high-resistivity SOI CMOS technology for high-volume cellular handset applications with adequate intermodulation and harmonic distortion performance. The design details and measurement results for a variety of RF switches with general-purpose input/output and mobile industry processor interface control interfaces, flip-chip/wire-bond packaging, and for various standards are discussed.

Design of D-PHY chip for mobile display interface supporting MIPI standard

This paper presents a MIPI (Mobile Industry Processor Interface) D-PHY (physical layer) analog part that meets the MIPI Alliance standard that supports high-speed (HS) transmitter (HS-TX) and receiver (HS-RX) modes as well as low-power (LP)-TX, LP-RX, and LP-contention detection (CD) modes. MIPI is a flexible, source synchronous serial interface standard connecting a host processor to display and camera modules on mobile devices. The standard supports signal levels of 1.2Vpp at 10Mbps in LP mode and 0.2Vpp at 80–1000Mbps in HS mode.In the design, we propose the use of special circuits: LP-TX controls the slew-rate and limits current with a push–pull driver that reduces electromagnetic interference, LP-RX maintains good noise immunity using a hysteresis comparator and a set/reset (SR) latch, HS-TX supports synchronous differential high-speed data transmission based on Scalable Low Voltage Signaling (SLVS), and HS-RX stably receives transferred data with DC variations and AC noise using a very-wide-common-mode range differential amplifier (VCDA). We implemented the MIPI D-PHY analog chip using 0.13μm CMOS process under a 1.2V supply. We found that the HS-RX block shows a jitter of less than 5% at 1Gbps and a power consumption of 0.74mW that is suitable for the standard.

P‐47: Integrating Multi‐PWM Devices into Source Driver for TFT‐LCD

AbstractThis paper proposes an Unequaled Single Source Driver (USSD) with multi‐chip topology to achieve large source driver outputs for WXGA resolution TFT‐LCD. The proposed driver used a multi‐domain power scheme in a chip, and was implemented by using a Bipolar CMOS DMOS (BCD) process. It incorporated a LVDS/MIPI combo receiver, timing controller, level shifter, charge pump, boost, inverter, and LED driver in a source driver to generate multiple power supply to the panel. Furthermore, the integral chip bus (iCB) with embedded code technique was used to synchronize data indices of color engines and control between the applications of multi‐chips. The proposed USSD was verified by a 15.6‐in WXGA TFT‐LCD, in which the 1 Gbps data rate was achieved by multi‐drop mobile industry processor interface.

모바일 기기 신호 인터페이스용 MIPI 디지털 D-PHY의 저전력 설계

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using CMOS process under 1.2V supply.

Unified dual mode physical layer for mobile CMOS image sensor interface

This paper presents a new unified dual-mode physical layer (PHY) architecture that can handle both of Mobile Display Digital Interface (MDDI) and Mobile Industry Processor Interface (MIPI) in high speed mobile display application. For this, we propose a wide operation range differential Low Voltage Differential Signal (LVDS) pairs which can simultaneously handle MDDI packet and sub-LVDS MIPI stream high speed serial data. In addition, the strobe pair in MDDI mode can be used as the high speed clock transmission lane in MIPI mode with some circuit techniques such as interoperation repeater circuit and low jitter input dual mode buffer. After protocol level processing, each unpacked image data are easily connected to parallel interface for system compatibility. Therefore, this unification is very useful for an embedded camera module in mobile phone application. Several experimental results under different electrical conditions verify the good operation of the proposed architecture. The image test under two different standard Mega pixel image sensors with the random data of about 1-Gpbs shows that the unified structure works well for both MDDI and MIPI.

A multi-lane MIPI CSI receiver for mobile camera applications

In this paper, we present a multi-lane Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI) receiver which is suitable for high-resolution camera and High-Density (HD) video applications. The presented receiver is designed to achieve parallel processing so that it reduces dynamic power consumption for multi-lane configuration. In order to facilitate parallel processing, we propose two techniques for the multi-lane receiver. The presented design receives data at the maximum rate of 4Gb/s and is verified in a standard CMOS technology.