Abstract
A 20-Gbps receiver bridge chip featuring auto-skew calibration and continuous-time linear equalization is proposed to support the mobile industry processor interface D-PHY version 2.0 specification with four data lanes and one clock lane. The proposed receiver bridge chip performs byte synchronization and 1-to-8 deserialization for converting high-speed scalable low-voltage signals into low-speed low-voltage complementary metal-oxide semiconductor signals. The proposed auto-skew calibration has a simple architecture and is insensitive to dynamic noise owing to the use of the multiple bits supplied from the deserializer as a result of the phase detector for the skew calibration. It is performed via a four-step sequential process to use the minimum time delay. The proposed receiver bridge chip is implemented using a 0.11 $\mu \text{m}$ CMOS process with a 1.2 V supply. The measured peak-to-peak time jitter of the signal recovered using the proposed receiver is 50 ps at a data rate of 5.0 Gbps/lane on a printed circuit board FR-4 10 inch channel. The proposed skew calibration reduces the time skew among the four data lanes and one clock lane to less than 10 ps.
Published Version
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