Μm SiGe BiCMOS Technology Research Articles

A Digital Controlled Accurate Linear-in-dB Variable Gain Amplifier Based on Current-Steering Structure with Compensation Circuit

The paper proposes a radio frequency front-end ultra-wideband variable gain amplifier (VGA) which is based on improved current-steering topology. The design is implemented in Tower Jazz 0.18 μm SiGe BiCMOS technology. Adding the gain compensation circuit broadens gain dynamic range, and introducing the emitter degeneration capacitor broadens the bandwidth of a typical current-steering topology. Moreover, the digital control function is obtained from the digital-to-analog converter circuit. Also, the input and output matching circuits are designed for testing. The measurement results show that the designed VGA achieves a gain dynamic range of 31 dB stepped by 1 dB from 8 to 18 GHz. Furthermore, input and output return losses are both lower than − 10 dB, and output 1 dB compression point is − 19.6 dBm ~ − 17 dBm at the highest gain stage. The VGA’s DC power consumption is about 14 mA from a 3.3 V supply, and it occupies a chip area of just 0.56 mm2.

Design of Differential Variable-Gain Transimpedance Amplifier in 0.18 µm SiGe BiCMOS

This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm.

An Edge-Coupled Marchand Balun With Partial Ground for Excellent Balance in 0.13 μm SiGe Technology

An edge-coupled meandered three-coupled-line Marchand balun with a partial ground plane implemented in 0.13 μm SiGe Bi-CMOS technology is presented in this brief. The balance performance of the designed balun is significantly improved by creating a `no ground plane' beneath the coupledline structure, which is demonstrated by simulating two baluns: one with a partial ground and the other with a solid ground underneath. The measured amplitude and phase imbalances are less than 0.4 dB and 2.5°, across the 3-dB bandwidth from 21.5 to 95 GHz, surpassing previously reported results of edge-coupled Marchand baluns. The balun occupies 230 μm × 370 μm.

An Area-Efficient and Programmable 4 × 25-to-28.9 Gb/s Optical Receiver with DCOC in 0.13 µm SiGe BiCMOS

In this paper, we present an area-efficient noise-optimized programmable 4 × 25-to-28.9 Gb/s optical receiver. Both high- and low-power modes are available for the receiver to meet different requirements. Emitter degeneration provides the input transimpedance amplifier (TIA) stage with improved stability. The noise of the TIA with emitter degeneration is analyzed, and an improved noise optimization method for the TIA is proposed. A sink current source with emitter degeneration in a DC offset cancellation (DCOC) loop reduces the noise introduced by the DCOC circuit. Moreover, with parasitic capacitor utilization in the DCOC loop and capacitive emitter degeneration in the variable-gain amplifier (VGA) stage, the chip area is minimized. Fabricated in a 0.13 µm SiGe BiCMOS technology, the receiver achieved a small area of 0.54 mm2 per lane. The measured bit error rate (BER) is 10−12 with input signal varying from 110 μApp to 1150 μApp. The one-lane power dissipation values in the low-power and high-power modes are 84.97 mW and 123.75 mW, respectively.

一款2 G/s采样率20 GHz带宽主从式跟踪保持电路设计研究

A fully-differential master-slave track-and-hold amplifier (MS-THA), with 20 GHz bandwidth is designed and fabricated using 0.13 μm SiGe BiCMOS technology. The MS-THA employs conventional switched-emitter-follower (SEF) as track-and-hold core circuit, Cherryhooper circuits as band-boosting of input buffer and output buffer. To verify the validity of the above circuits, a single-stage THA is designed together with the MS-THA. Operating with a single +3.3 V supply, 0 V input direct-voltage, 2 G/s sampling and −3 dBm input power, the MS-THA achieves a single-ended spurious free dynamic range (SFDR) of less than −23.5 dB at frequency of up to 20 GHz, and total power consumption of about 300 mW.

A 30Gbps power-efficient dual-loop adaptive equalizer in 0.13 ​ ​μm SiGe BiCMOS technology

A 30Gbps power-efficient equalizer including an adaptive loop combined with a direct current offset cancellation (DCOC) loop is presented in this paper. Based on spectrum balanced technique, the adaptive loop applies signal strength indication (SSI) circuit to detect the low and high frequency power of equalized signal. After that, peaking gain of equalizer is adjusted according to detection value of SSI circuits. With the help of operation amplifier and trans-conductance amplifier, the proposed DCOC loop decreases the mismatch error. By applying inductive peaking and RC-degeneration technique, the continuous time linear equalizer (CTLE) compensates for channel insert loss in equalizer. A double-fT cell with inductive peaking technique is utilized to expand the bandwidth. To reduce effect of parasitic capacitor from output buffer, equalized signal is reshaped by three-stage cascaded limiting amplifier. Benefiting from excellent impedance matching by employing micro-strip and peaking inductor in terminal, the maximum channel loss equalized at 14 ​GHz is −18dB. The maximum reflection loss of Sdd11 and Sdd22 measured at 42 ​GHz and below are -9dB. Peak-peak jitter of 11.33ps is measured at 30Gbps after equalization. Meanwhile, only 53 ​mW power dissipation is consumed with a power supply of 1.8 ​V. Fabricated in 0.13 ​ ​μm SiGe BiCMOS technology, this chip only occupies active area of 0.32 ​mm2.

Design a monolithic wideband balun for mixers and amplifiers based on SiGe BiCMOS technology

In this paper a monolithic balun for mixers and amplifiers based on BiCMOS Technology presented on chip integrated balun based on 0.25 μm SiGe BiCMOS technology. monolithic microwave integrated circuit is designed by the passive double-balanced mixers with the help of resistive field effect transistor topology. The formation of integrated monolithic balun is a cross coupled and asymmetric. The performance of monolithic balun is measured over the range of 0–5 GHz frequency range. This balun is having the specification of conversion gain Gc is greater than − 10 dB, RF IC isolation is greater than 25 dB, LO–RF and LO–IF isolation is greater than 40 dB, return losses at IF and RF ports are better than − 10 dB. In terms of dimensions we uses the length and width of the periphery 800 × 600 μm. For layer conductance we uses the substrate as Silicon TopMetal2.

A SiGe BiCMOS phase shifter based on quarter‐wave coupled resonators

This work presents the first example of monolithically integrated phase shifter based on a pass-band filter architecture. The proposed configuration was realized mapping a classical quarter-wave coupled filter circuit into its lumped element equivalent. Phase control is achieved by controlling the pass-band through tunable tanks employing varactor diodes. A demonstrator was prototyped in the 24 GHz ISM band using a 0.25μm SiGe BiCMOS technology. Experimental results show 180° of phase range and maximum transmission losses of 8 dB. The main feature of this configuration is that it allows controlling the transmission losses by design and that its size is extremely compact.

A 22‐37 GHz low noise amplifier with 2.8 dB mean noise figure and +22.9 dBm output 3rd‐order intercept point for 5th generation applications

AbstractThis paper presents a wideband 22‐37 GHz low noise amplifier (LNA) realized in a 0.25 μm SiGe BiCMOS technology. The design incorporates additional noise matching between the cascode transistors to minimize the noise figure (NF) degradation. The second stage incorporates an active balun architecture with a tail inductor to improve the common‐mode rejection ratio (CMRR). To extend the bandwidth, a capacitive feed forward path is added at the second stage. The LNA presents a minimum in‐band NF of 2.3 dB from 22‐37 GHz. The achieved 3 dB‐gain bandwidth is larger than 15 GHz, with a peak gain of 20.8 dB at 28 GHz. The output 3rd‐order intercept point (OIP3) is +22.9 dBm for a total power consumption of 94 mW. The area of the core circuit is 0.35 × 0.47 mm2. To the author's knowledge, the LNA shows the best overall performance compared to the existing silicon‐based LNAs.

A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

A SiGe 3-stage LNA for automotive radar application from 76 to 81 GHz

This paper presents the simulation results of the W-band 3-stage low noise amplifier which is designed in 0.13 μm SiGe BiCMOS technology. The LNA achieves a peak S21 of 24.1 dB and noise figure of 6 dB at 80 GHz with 3 dB bandwidth of 14 GHz from 73 to 87 GHz. S11 is better than 11 dB. The simulated input 1 dB compression point is –23 dBm at 80 GHz with low power consumption of 26 mW from 1.2 V voltage supply. Layout area is 0.36 mm2.

Particularities of complex-functional monolithic integrated circuits post-layout simulation

This paper presents a silicon-based complex-functional monolithic microwave integrated circuits (MMICs) design methodology. Post-layout simulation stage particularities are discussed. Pre-tapeout functionality verification results of the C-band phase and amplitude control MMIC based on 0.18 μm SiGe BiCMOS technology are also presented.

Transmitters and receivers in SiGe BiCMOS technology for sensitive gas spectroscopy at 222 - 270 GHz

This paper presents transmitter and receiver components for a gas spectroscopy system. The components are fabricated in IHP’s 0.13 μm SiGe BiCMOS technology. Two fractional-N phase-locked loops are used to generate dedicated frequency ramps for the transmitter and receiver and frequency shift keying for the transmitter. The signal-to-noise ratio (SNR) for the absorption line of gaseous methanol (CH3OH) at 247.6 GHz is used as measure for the performance of the system. The implemented mixer-first receiver allows a high performance of the system due to its linearity up to an input power of -10 dBm. Using a transmitter-array with an output power of 7 dBm an SNR of 4660 (integration time of 2 ms for each data point) was obtained for the 247.6 GHz absorption line of CH3OH at 5 Pa. We have extended our single frequency-band system for 228 – 252 GHz to a 2-band system to cover the range 222 – 270 GHz by combining corresponding two transmitters and receivers with the frequency bands 222 – 256 GHz and 250 – 270 GHz on single transmitter- and receiver-chips. This 2-band operation allows a parallel spectra acquisition and therefore a high flexibility of data acquisition for the two frequency-bands. The 50 GHz bandwidth allows for highly specific and selective gas sensing.

W-band voltage-controlled oscillator design in 130 nm SiGe BiCMOS technology

The paper presents design flow and simulation results of the W-band fundamental voltage-controlled oscillator in 0.13 μm SiGe BiCMOS technology for an automotive radar application. Oscillator provides fundamental oscillation range of 76.8 GHz to 81.2 GHz. According to simulation results phase noise is –89.3 dBc/Hz at 1 MHz offset, output power is –5.6 dBm and power consumption is 39 mW from 3.3 V source.

A 71–76 GHz wideband receiver front-end for phased array applications in 0.13 μm SiGe BiCMOS technology

This paper presents the design of a millimeter-wave wideband receiver front-end in a 0.13 \(\upmu\)m SiGe BiCMOS technology for phased array applications. The receiver front-end is suitable for a phased array time-division duplexing communication system where both the transmitter and the receiver share the same antenna. The monolithic microwave integrated circuit front-end comprises of quarter-wave shunt switches, a low-noise amplifier (LNA), an active phase shifter and a buffer amplifier. The quarter-wave shunt switch is designed using reverse-saturated SiGe HBTs. The transformer-based LNA utilizes a common-emitter amplifier at the first stage and a cascode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The designed switch is incorporated in the input matching network of the LNA. The active phase shifter consists of variable gain amplifiers driven by a polyphase filter-based quadrature generator. The receiver front-end achieves a measured gain of 18.5 dB and a noise figure of 9 dB with a 3 dB bandwidth of 23 GHz from 56 to 79 GHz. The receiver phase can be tuned continuously from 0\(^{\circ }\) to 360\(^{\circ }\). An output referred 1-dB compression point of \(-\) 7.4 dBm is achieved at 70 GHz. The receiver consumes 116 mW of DC power and occupies a core area of \(1800\,\upmu {\text {m}} \times 475\,\upmu {\text {m}}\).

3-Path SiGe BiCMOS power amplifier on thinned substrate for IoT applications

This paper reports a transformer-based integrated class-A Differential Power Amplifier (DPA) for the Internet of Things (IoT) applications. The proposed 5–6 GHz fully integrated differential PA is fabricated in a cost-effective 95 GHz-fmax, 0.25 μm SiGe BiCMOS technology (IHP process SGB25V). The amplifier utilizes a thin Si chip with a thickness of 45 μm in order to be embedded into flexible electronic foil systems. Several key RF performance parameters of the DPA with different substrate thicknesses are evaluated at the wafer level. The measurement results indicate that the DPA shows no significant S-parameters degradation due to the thickness differences. The measured gain center frequency is shifted about 300 MHz towards higher frequencies after thinning because of the image mirror currents within the conducting material at the backside of the chip. The DPA achieves 10.65 dB and 9.7 dB small-signal gain at 5.5 GHz before and after thinning, respectively. The PA delivers an output power of +9 dBm before and +8.1 dBm after thinning process at Pin = −1.3 dBm. The simulated 1 dB compression point occurs at +10.76 dBm output power with a PAE of 15%.

TunableQ-enhanced LC dual-band filtering at microwave frequencies in 0.13 µm SiGe BiCMOS

AbstractThis paper presents an activeQ-enhanced LC dual-band band-pass filtering approach using parallel synthesis techniques at X- and Ku-bands in 0.13µm SiGe BiCMOS technology. By employing two independently tunable parallel LC-tanks with either in-phase and out-of-phase addition, independently tunable dual-band filtering is achieved. For higher out-of-band (OOB) attenuation, subtraction of the two 2nd-order bandpass filter is implemented. The two bands are independently tunable in terms ofQand center frequency. The dual-band filter at 9.7 GHz and 13.9 GHz achieves a normalized dynamic range of 165–154.5 dB.Hz with an OOB attenuation of >50 dB below 3 GHz. In between the two bands, the attenuation is 22 dB when the two passbands have 200 MHz bandwidth each. The total group delay is 0.8 ns and 1.9 ns forQof 20 and 50, respectively. The filter achieves better OOB rejection with wider band channels at X- and Ku-bands compared with state of the art integrated filters. The filter consumes 115–130 mW of DC power. The core die area is 0.53 × 0.7 mm2.

Towards Breath Gas Analysis Based on Millimeter-Wave Molecular Spectroscopy

Abstract Breath gas analysis is a promising non-invasive tool for medical diagnosis as there are thousands of Volatile Organic Compounds (VOCs) in human breath that can be used as health monitoring markers. Millimeter-wave/terahertz molecular spectroscopy is highly suitable for breath gas analysis due to unique fingerprint spectra of many VOCs in that frequency range. We present our recent work on sensor systems for gas spectroscopy based on integrated transmitters (TX) and receivers (RX) fabricated in IHP’s 0.13 μm SiGe BiCMOS technology. For a single-band system, spectroscopic measurements and beam profiles are presented. The frequency is tuned by direct voltage-frequency tuning and by a fractional-n PLL, respectively. The spectroscopic system includes a folded gas absorption cell with gas pre-concentration abilities demonstrating the detection of a 50 ppm mixture of ethanol in ambient air corresponding to a minimum detectable concentration of 260 ppb. Finally, the design of a 3-band system covering frequencies from 225 to 273 GHz is introduced.

A 2.1 GHz 30 dBm power amplifier in 0.18 μm SiGe BiCMOS process

AbstractA cascode power amplifier (PA) fabricated in 0.18 μm SiGe BiCMOS technology is presented. The cascode structure is used to provide high voltage gain and high output power. To prevent the negative impact of bond wire, the pseudo‐differential structure is used to provide a virtual ground for signal. Adaptive bias circuit provides stable voltage bias to the base of common‐emitter. With the combination of two completely symmetrical PA units, the whole PA achieves its saturated output power of 30.62 dBm and PAE of 31.75% at 2.1 GHz, and the small signal gain is 26.19 dB.

Design of 0.35–1.5 GHz 16‐input and 8‐output switch matrix with 5 × 5 chessboard structure

This Letter presents a 0.35–1.5 GHz 5 × 5 switch matrix chip with a chessboard structure. In the proposed structure, by reassigning the position and switch mode of 25 passive switch grids which almost consume no DC power, the switch matrix can choose and transmit any eight of 16 input signals to the output ports on four directions at the same time. Throughput and the expansion ability of the switch matrix are markedly improved by flexibly choosing a signal path and reusing the switch grids. Besides, wideband gain compensation circuit modules and gain equalisers are used to compensate for insertion loss and gain flatness of the switch matrix. Fabricated by 0.18 μm SiGe BiCMOS technology, the measured highest insertion gain of a signal path is 10 dB. Meanwhile, insertion gains of all signal paths are higher than −6 dB, and isolations of all signal paths are better than 40 dB.