Mixed-signal Test Research Articles

A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing

A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing

Experimental Validation of a Compact Pinhole Latent Defect Model for MOS Transistors

Currently, the semiconductor industry requires test escape levels that approach the ppb level for application domains, such as automotive. Such quality levels, however, can only be reached if latent defects are screened out, as they have become the major bottleneck in analog and mixed-signal IC testing. Latent defects can be activated using accelerated aging, but this procedure has several drawbacks. Most notably, activation can move latent defects to the product lifetime that, otherwise, would not even have expressed themselves. Therefore, methods are needed that allow the detection of these defects without using activation. Developing such methods, however, has been hampered by the lack of compact latent defect models that allow simulating circuits affected by this type of defect. This article alleviates this problem by experimentally validating a recently presented compact model for latent defects and establishing the practical range of model values that should be used in simulations. The experiments performed on a 0.35- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> technology consist of characterizing transistors containing latent defects that have been artificially introduced by etching pinholes in their gate. The measurement results corroborate that the drain current in transistors with defects increases with the area and depth of the defect, and that this behavior can be accurately modeled using an effective <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{ox}$ </tex-math></inline-formula> value.

Embedded Radiation sensor with OBIST structure for applications in mixed signal systems

Oscillation based testing (OBT) has proven to be a simple and effective test strategy for numerous kind of circuits. In this work, OBT is applied to a radiation sensor to be used as a VLSI cell in embedded applications, implementing an oscillation built-in self-test (OBIST) structure. The oscillation condition is achieved by means of a minimally intrusive switched feedback loop and the response evaluation circuit can be included in a very simple way, minimizing the hardware overhead. The fault simulation indicates a fault coverage of 100% for the circuit under test.Keywords: fault simulation, mixed signal testing, OBIST, oscillation-based test, VLSI testing.

TIME-INTERLEAVED MIXED-SIGNAL TEST CORE DIGITIZERS

System-on-Chip (SoC) is one of the main driving forces that have been re-shaping the consumer electronics industry. The SoC alternative to conventional systems design is growing in popularity as the device packing densi escalates due to the evolution of semiconductor technology. Moreover, the decrease in semiconductor feature size is permitting the increase of clock frequencies and component operating speed. These advancements necessitate the integration of system components due to package parasitics and lengthy interconnect. Furthermore, SoC devices offer a cheaper and more compact solution to the consumer electronics industry.An integrated mixed-signal test core approach to SoC data acquisition is a valued alternate solution to many of the problems involving conventional test. One such test core data conversion architecture incorporates a sub-sampling algorithm known as the multipass method of digitization. This method occupies a very small silicon area in exchange for an increased data conversion time. Time-interleaved test core digitizers provide the capability to reduce test time, increase sampling frequency and increase signal bandwidth. As an implicit result of this compact circuit and multipass processing methodology, significant reductions in noise and spurious tones are observed.

An adaptive simulation framework for AMS-RF test quality

Ensuring the quality of a circuit implies ensuring the quality of test. Despite the fact that performance-based testing has been the golden standard for Analog, Mixed-Signal and RF test for decades, high-reliability markets like automotive have found that functional test leaves some potential defects undetected that can produce in-field failure. There is thus a push towards defect-oriented testing which, in turn, calls for an efficient defect simulation framework. This paper presents a statistical adaptive defect simulation based on likelihood-weighted random sampling to evaluate the quality of AMS-RF tests in terms of defect coverage and fault escape. The adaptive loop takes a decision at each new defect simulation on whether it is more efficient to assess the defect coverage or the fault escape rate of the test under evaluation, as a function of the desired targets for these two metrics. Several decision criteria are proposed and validated by simulation of a complete IC for different tests.

Stochastic EMI Noise Model of PCB Layout for Circuit-Level Analysis of System in IoT Applications

In this article, a simple noise model is proposed for analysis of electromagnetic interference (EMI) on printed circuit board (PCB) layout of an electronic device. In Internet of Things (IoT) applications, devices are connected wirelessly and this results in electromagnetic pollution in environment. This may degrade the performance and/or even stop the operation of present devices in the shared setting. Internal and external interferences, due to near- and far-field are modeled as two independent random voltage sources. These sources can be treated as noise source like the thermal noise one in circuit noise analysis including the physical layout and electromagnetic threat. As a quantitative measure of electromagnetic pollution, EMI environment temperature is defined based on aggregation of waves emitted from different wireless device antennas. Also, for the PCBs, a stochastic EMI radiation resistance is defined based on system components’ placement and layout. This resistance can be used as an effective measure of interference potential severity for system PCB in an environment. The model is verified by specific designed and fabricated mixed-signal test board. The comparison between analytic model and measurement results shows a moderate accuracy which is acceptable in most predictive electromagnetic compatibility (EMC)/EMI verification. The proposed model is valid up to some GHz for conventional PCB physical parameters.

Design an Identification Function to Reduce the Computational Resources on the Testing Process of an Analog Electronic Circuit

In modern electronic circuits, imperfectness in the technological process can cause errors in reaching the correct values of the functional parameters. In order to solve this problem, a novel approach of analog and mixed-signal circuit testing methodology is used. The presented approach allows the testing complexity to be reduced and the testing time to be decreased. For this paper, selected signal features were designated from the transient output signal response. Using regression models with the extracted signal features, the functional parameters of a circuit were determined. An evolutionary determination of the regression models enabled the efficiency of the identification process to be maximized. The proposed methodology is presented for an exemplary CMOS Dickson charge pump circuit.

Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation

This paper presents the design of linear ramp generator and digital BIST for an on-chip ADC testing. It replaces the costly and time-consuming traditional mixed signal test methods like DSP-based testing, ATE, etc. The proposed on-chip analog ramp generator uses only a few transistors to generate linear ramp signal. A TIQ comparator based 8-bit flash ADC is taken under test. The output response of the ADC is analyzed in the digital BIST to measure the primary nonidealities affecting the linearity and accuracy of the data conversion. In testing, ADC generates the digital data sequence as a test pattern in response to the ramp input while digital BIST estimates the conversion error. This method does not require DAC and any additional components which increase the area overhead of ADC test. The complete design of ramp generator is integrated with TIQ flash ADC and verified in 0.18[Formula: see text][Formula: see text]m CMOS technology with 1.8[Formula: see text]V of the power supply and 100[Formula: see text]kHz of the input frequency. Measurement of nonidealities shows that the design of an 8-bit flash ADC has good accuracy in data conversion with the differential nonlinearity of [Formula: see text]0.24/[Formula: see text]0.17[Formula: see text]LSB and integral nonlinearity of [Formula: see text]0.44/[Formula: see text]0.04[Formula: see text]LSB.

Guest Editorial: Special Issue on Analog, Mixed-Signal, and RF Testing

Guest Editorial: Special Issue on Analog, Mixed-Signal, and RF Testing

A 130 nm 165 nJ/frame Compressed-Domain Smashed-Filter-Based Mixed-Signal Classifier for “In-Sensor” Analytics in Smart Cameras

To avoid data deluge at the back end, it is imperative that advanced sensor nodes perform “in-sensor” processing to extract relevant features from data. We propose a compressed-domain smashed-filter-based object recognition system and measurements from a 130 nm mixed-signal test chip to demonstrate reconfigurable and ultra-low power operation. We measure greater than 90% accuracy in object localization with 165 nJ energy per frame on image data sets.

Guest Editorial: Analog, Mixed-Signal and RF Testing

Guest Editorial: Analog, Mixed-Signal and RF Testing

Multi-Directional Space Tessellation to Improve the Decision Boundary in Indirect Mixed-Signal Testing

One of the most challenging aspects in nowadays microelectronics industry is production test and verification of mixed-signal circuits. In order to cope with some of the drawbacks encountered in this scenario, researchers have found alternate test as a promising solution in achieving such endeavor. This work prospects the possibilities of using space tessellations along multiple directions in order to improve the test decision boundary definition in the alternate measure space. The proposed method is able to reduce false positive test outcomes, i.e. test escapes, with acceptable penalty in test yield loss metric. The key idea presented in this work is to use an ensemble of octrees, each of them tessellating the plane along different directions. Such tessellations create a refinement in the non linear test decision boundaries without the need of including extra circuit samples. The tree ensemble, together with a strict test decision criterion, serve as a classifier during the production testing phase. The proposed multi-directional ensemble tessellation strategy has been applied to test a band-pass Biquad filter affected by parametric variations. The proposed method has reported promising simulation results in lowering the test escapes metric as compared to a single octree classifier. The computational overhead of evaluating several octrees is insignificant since 2n-tree data structures are traversed efficiently. The octree ensemble technique has also been compared against a classic specification guard-banding technique reporting better test yield loss metrics for the same test escape target.

Guest Editorial: Analog, Mixed-Signal and RF Testing

Guest Editorial: Analog, Mixed-Signal and RF Testing

Focus on spectroscopy and photonics

Focus on spectroscopy and photonics

Fault detection in analog and mixed-signal circuits by using Hilbert–Huang transform and coherence analysis

Using Hilbert–Huang transform (HHT) and coherence analysis, a signature extraction method for testing analog and mixed-signal circuits is proposed in this paper. The instantaneous time–frequency signatures extracted with HHT technique from the measured signal of circuits under test (CUT) are used for faults detection that is implemented through comparing the signatures of faulty circuits with that of the fault-free circuit. The coherence functions of the instantaneous time–frequency signatures and its integral help to test faults in the faulty dictionary according to the minimum distance criterion. The superior capability of HHT-based technique, compared to traditional linear techniques such as the wavelet transform and the fast Fourier transform, is to obtain the subtle time-varying signatures, i.e., the instantaneous time–frequency signatures, and is demonstrated by applying to Leapfrog filter, a benchmark circuit for analog and mixed-signal testing, with 100% of F.D.R (fault detection rate) in the best cases and with the least 24.2% of F.L.R. (fault localization rate) with one signature.

Test setup for reliability studies of DDR2 SDRAM

A DDR2 DRAM test setup is developed and implemented on the Griffin III ATE test system from HILEVEL Technologies. The test system provides a raw platform for performing various mixed signal and digital tests. In order to configure patterns easily in a vector format, a software platform is developed to manage test patterns according to the user's analysis needs. As examples, retention test patterns with disabled self-refresh are applied to 2Gbit DDR2 SDRAM of two different DRAM vendors. The devices are characterized in respect to their intrinsic leakage and data retention behavior under the influence of stress conditions such as temperature or access algorithm. The tests are automated and test data is logged for an off-line data analysis. Data is recorded before and after solder simulation steps in order to observe a retention time degradation.

Analog and Mixed Signal Test Method based on OBIST Technique

paper describes a test method for analog and mixed signal device at very low cost and based on OBIST (oscillation test) method. This method is built-in self test method appropriate for functional and structural testing of analog and mixed signal circuit. In test mode, the test circuit is converted into an oscillator. Then faults inside the test circuit that cause an affordable deviation of the oscillation frequency from its value are detected. Through this test method, no test vector is required to apply. Therefore in this test technique, the test vector generation drawbacks are eliminated and also the test time is reduced because limited number of oscillation frequencies is evaluated for each test circuit. This characteristic implies that Oscillation-test methodology is very attractive for further wafer-probe testing as final production testing. During this paper, the simulation results of this test method has been provided and verified throughout some examples like CMOS inverter and FET (field effect transistor).

Introducing a course in test and measurement at Texas A&amp;M University - Kingsville

The purpose of this article is to describe a graduate level electrical engineering course offered at Texas A&M University - Kingsville (TAMUK). Mixed-Signal IC Test and Measurement (T&M) is a special topics course designed to introduce electrical engineering students to the technical issues involved in integrated circuit (IC) high-volume, high-throughput, production testing. Universities around the world offer courses and programs in instrumentation and measurement (I&M) as part of their engineering curricula [1] - [4]. Because I&M is a broad multi-disciplinary field, these courses have tended to emphasize transducers, controls, statistics, signal analysis, and data conversion [5] - [8]. In this theoretical framework, this course is similar. However, in the context of application, this is different.

Designing nonlinearity characterization for mixed-signal circuits in system-on-chip

Long test times and the use of conventional automatic test equipment (ATE) makes conventional mixed-signal linearity performance testing costly. Diminishing test time of linearity test significantly reduces system-on-a-chip production test costs and, therefore, lessens total product manufacturing costs. Several low-cost linearity test methods have addressed this issue for a single-ended mixed-signal circuit testing. On the other hand, a low-cost test approach has rarely been proposed for differential mixed-signal circuits, due to a new class of test obstacles from differential circuits that are widely employed for high-speed I/O products. This paper presents a cost-effective self-test methodology to characterize the linearity performance of differential mixed-signal circuits in loopback mode. The proposed method precisely predicts the device-under-test (DUT) linearity specifications by building accurate DUT nonlinear polynomial models using spectral specifications from recent work. The test cost is significantly reduced by replacing conventional ATE with the proposed self-test platform and by reducing test time to a fraction of conventional testing time. Hardware measurement results validated the test performance of the proposed test scheme.

On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing

We propose an approach to design of an algebraic signature analyzer that can be used for mixed-signal systems testing. The analyzer does not contain carry propagating circuitry, which improves its performance as well as fault tolerance. The common design technique of a signature analyzer for mixed-signal systems is based on the rules of an arithmetic finite field. The application of this technique to the systems with an arbitrary radix is a challenging task and the devices designed possess high hardware complexity. The proposed technique is simple and applicable to systems of any size and radix. The hardware complexity is low. The technique can also be used in arithmetic/algebraic coding and cryptography.