Mixed-signal Test Research Articles

Bitstream-Driven Built-In Characterization for Analog and Mixed-Signal Embedded Circuits

The conventional analog and mixed-signal production testing of system-on-a-chip systems provides limited controllability and observability because automatic test equipment (ATE) access is limited to device under test (DUT) ballouts. More importantly, production mixed-signal testing, due to long test times and expensive ATE, represents a substantial portion of the total manufacturing costs. This brief presents a cost-effective and advanced-signature-based dynamic test method that uses a built-in self-test (BIST) platform that enhances the controllability and observability of mixed-signal embedded systems. The BIST platform includes a simple on-chip signature generator that comprises a clipper and a single-bit comparator. This brief precisely predicts the dynamic nonlinearity of individual mixed-signal circuits connected in a loopback configuration by clipping the loopback-path signal to efficiently give the loopback response a different weighting. The clipped behavior of the loopback-path signal is translated to a bitstream signature by the comparator. The signature and the loopback response allow us to efficiently split the loopback performance into individual DUT performances by solving the DUT characteristic equations using the on-chip digital-signal-processor core. Hardware measurements were performed to show that the proposed method can be practically applied in production.

Nonlinear Analysis of Mixed Signal Test Based on Graphic Program Design

In this paper, based on the parabolic interpolation function of nonlinear Lagrange, we establish the mathematical model of business translation graphical teaching method. In order to verify the availability and reliability of the model and algorithm, we test the performance of graphic business English translation platform. After testing the mixed signal of platform, the current with fault is lower than circuit without fault. The peak voltage of triangular wave is about-6V and 6V. According to the response curves of English translation circuit, different sequencers realize the parallel translation. It improves business English translation speed, and provides the technical reference for the innovation cultivation of business English talents.

Efficient and Accurate Testing of On-Chip ADC Based on ATE

The embedded digital-analog mixed-signal circuit testing has become one of the difficulties to be solved. In this paper, a SoC embedded ADC has been tested based on the Credence Gemini500 verification system. The testing method is studied and verified through the test experiment and results. This testing method is an important reference for general embedded IP core testing.

An Introduction to Mixed-Signal IC Test & Measurement [Book Review

"An Introduction to Mixed-Signal IC Test & Measurement," by Gordon Roberts, Frederich Taenzler and Mark Burns (ISBN: 978-0-19-979621-2) is an excellent guide to the mixed signal test frontier. It provides the reader with the theory of analog test, which is common in this kind of book, but also much information on the practical aspects of analog test, and, even more importantly, tells the reader the common mistakes to avoid. This practical focus puts this book above the vast majority of other texts. All too often a book will describe five different ways of achieving a task, using a historical approach, but never tell the reader which one has been found to be the best, and is thus commonly used in industry. All too many readers of books on digital testing might think that deductive fault simulation is being used somewhere. Such confusion is not a problem here. The reviewer says he has never seen a book which is as successful in combining the theoretical and practical, and in giving a hint about which method to use first in the midst of a large set of equations.

An Overview of Mixed-Signal Production Test from a Measurement Principle Perspective

In this article, a tutorial on the techniques and procedures used in a production test environment is presented. This overview is structured in such a way that the less experienced test engineer can learn about the common and various methods used in mixed-signal test. Various aspects related to test and their role in the manufacturing process of ICs are discussed. In fact, the paper starts off by motivating the need for testing and then describes the different methods: DC, AC, and dynamic testing as well as clocks, SerDes and RF testing. Design for Test (DFT) techniques are also described.

Analogue and Mixed-Signal Production Test Speed-Up by Means of Fault List Compression

Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. The purpose of this paper is to propose a novel fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. Criteria to partition the fault list in strata, and to identify representative faults are presented and discussed. A fault representativeness metric is proposed, based on an error probability. The proposed methodology allows different tradeoffs between fault list compression and fault representation accuracy. These tradeoffs may be optimized for each test preparation phase. The fault representativeness vs. fault list compression tradeoff is evaluated with an industrial case study—a DC-DC (switched buck converter). Although the methodology is presented in this paper using a very simple fault model, it may be easily extended to be used with more elaborate fault models. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.

Current State of the Mixed-Signal Test Bus 1149.4

This paper presents the current state of the IEEE standard for a Mixed-Signal Test Bus 1149.4 and examines proposed modifications and alternatives. The standard was published in 2001 and got its first major update in 2011 which included description language support. Although the standard has not gained high usage in the electronics manufacturing industry, research has been undertaken to improve its usability. The main research topic has been the test methods for discrete components and analog circuits but the usage of the analog test environment for various applications has also been considered. The proposed modifications for 1149.4 aim to exceed the current limitations of the standard such as the inability to perform RF testing or to access problems in multichip packages. The alternatives for the standard are examined, focusing on other testability standards and also emerging standards such as IJTAG. The alternative test methods and standards cannot directly replace the 1149.4, especially on board level mixed-signal testing.

Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing

Test cost has gradually become a major portion of the overall product cost for System-on-Chips (SoCs). Developing efficient methods to test and debug analog, mixed-signal, and radiofrequency (RF) circuitries is of particular interest due to their lengthy test times and increased complexity. In the past, mixedsignal/RF circuits were built as stand-alone chips, so test developments were geared toward characterizing individual building blocks. With increased integration, the controllability and observability to these mixed-signal/RF circuits has become limited. As a result, built-in self-test (BIST) and design-fortestability (DfT) modifications that can help reduce test time and facilitate silicon debug have gained more attention. This special issue collects 16 state-of-the-art solutions for testing various mixed-signal, RF, and MEMS circuits. The first four papers propose BIST techniques for on-chip mixed-signal, RF, and MEMS modules. In paper 1, Zhang et al. develop an amplitude detector that transforms highfrequency signals into DC/low-frequency components. They then infer high-frequency circuit performance from detectors’ output and show that both the systemand component-level performances can be tested with great accuracy. In paper 2, Hung and Hong propose a BIST scheme for ADCs where the control signals are wirelessly transmitted from an HOY tester. They show that the BIST test results align well with those produced by conventional methods. In paper 3, Kim and Abraham propose a BIST scheme for testing the setup and hold time of the memory interface. They use a static mode test method to determine pass/fail on the timing specifications, as well as a dynamic mode test method to measure the amount of timing mismatch. In paper 4, Sarraf et al. develop an adaptive technique based on pseudo-random sequences for testing and calibrating MEMS-based accelerometers and gyroscopes. Papers 5 to 7 focus on techniques for generating accurate and low-cost test signals. In paper 5, Duan et al. incorporate the “stimulus error identification and removal” (SEIR) algorithm into their BIST solution so that they can test high-resolution ADCs without using high precision stimuli, thereby saving cost. For applications that require time or frequency domain test stimulus, in paper 6, Tsai et al. develop a time/frequency-domain signal generator using a sigma-delta modulator, a digital-to-frequency or a digital-totime converter, and a phase locked-loop. Testing ADCs usually requires high-precision signal generation. In paper 7, Wakabayashi et al. propose an algorithm for generating low distortion sine-wave signals using low-resolution (hence, low cost) waveform generators. Papers 8 to 12 enhance observability of internal analog signals. In paper 8, Kulovic and Margala introduce a technique for on-chip voltage measurement. On-chip voltages are first converted to the time domain, and subsequently, to the frequency domain using a centralized time-to-digital converter. The distributed manner of voltage-to-time conversion enables concurrent voltage measurement. In paper 9, Maltabas et al. propose a current sensor that is suitable for IDDQ measurement. In paper 10, Gomez et al. exploit the relationship between device transconductance and static power dissipation to observe process variations. In paper 11, Dasnurkar and Abraham propose a built-in current sensor that is suitable for measuring internal bias currents. Responsible Editor: H.-M. Chang

Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications

This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. Two integrated demonstrators are presented to show the feasibility of the approach. The proposed generation technique is based on a modified analog filter that provides a sinusoidal output as the response to a DC input. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. The demonstrators—a continuous-time generator and a discrete-time one—have been integrated in a standard 0.35 μm CMOS technology. Simulation results and experimental measurements in the lab are provided, and the obtained performance is compared to current state-of-the-art on-chip generation strategies.

Mixed-signal SoC test based on task flow

Mixed-signal SoC test based on task flow

Enabling Remote Testing: Embedded Test Controller and Mixed-signal Test Architecture

Remote testing requires embedded test infrastructure, consisting of communication, test control and test access. This article presents an embedded test solution for a low-frequency audio board. Supporting analog testing, the solution consists of a measurement and calculation method for passive component characterization, analog test bus solution and an embedded test controller for controlling embedded tests and providing test stimuli. Moreover, the solution, which supports the presented test plan, was compared to a test plan supporting traditional testing. It was found that the embedded test solution provided a 29% test coverage of the audio board components and substituted flying probe testing included in the traditional test plan. Besides such benefits as improved fault diagnostics and lower manufacturing costs, the paper also discusses the drawbacks of the presented solution, including reduced measurement accuracy. This paper also presents a correction to a previously presented passive component measurement and calculation method.

Industry-Oriented Laboratory Development for Mixed-Signal IC Test Education

The semiconductor industry is lacking qualified integrated circuit (IC) test engineers to serve in the field of mixed-signal electronics. The absence of mixed-signal IC test education at the collegiate level is cited as one of the main sources for this problem. In response to this situation, the Department of Electrical and Computer Engineering at the Ohio State University, Columbus, has partnered with Texas Instruments to establish an IC test-engineering-oriented course. The course objectives are to familiarize students with industrial testing techniques and to help students obtain the fundamental skill sets required to be competent mixed-signal IC test engineers. A novel laboratory pedagogy is developed to achieve these objectives. The results of the classroom assignments and the feedback provided by students, faculty, and industry representatives indicate that the approach has successfully achieved these goals.

Low Cost MIMO Testing for RF Integrated Circuits

Multiple-input-multiple-output (MIMO)-based systems are extremely popular as they offer data rates as twice as fast as currently available systems. Their testing becomes more complicated due to the increased number of RF paths. This increases the overall test cost of these devices both in terms of test time and instrumentation cost. In this paper, we demonstrate a low cost MIMO test solution which targets critical specifications that are fundamental to the MIMO system operation, such as gain, IIP3, and phase imbalances between the RF paths. Our test methodology measures these parameters with a single test setup that enables the calculation of these performance parameters. Using the proposed test method, RF MIMO systems can be tested using a mixed signal tester, and on-board circuitry within a reasonable accuracy. Both simulation and measurement results confirm the high accuracy and repeatability of our test technique.

Noise Isolation in Mixed-Signal Systems Using Alternating Impedance Electromagnetic Bandgap (AI-EBG) Structure-Based Power Distribution Network (PDN)

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents efficient noise isolation and suppression method in mixed-signal systems using alternating impedance electromagnetic bandgap (AI-EBG) structure-based power distribution network (PDN). Currently, split planes are used for isolation in mixed-signal systems for isolating sensitive RF/analog circuits from noisy digital circuits. However, split planes show good isolation only at low frequencies due to electromagnetic coupling through the gap. The AI-EBG structure-based PDN presented in this paper provides excellent isolation (<formula formulatype="inline"><tex Notation="TeX">$-80~{\hbox {dB}} \! \sim \! -100~{\hbox {dB}}$</tex></formula>) in the frequency range of interest by suppressing almost all possible electromagnetic modes. The AI-EBG structure has been integrated into a mixed-signal test vehicle to demonstrate the isolation level achievable. The ability of the AI-EBG structure to suppress switching noise has been quantified in this paper. The AI-EBG structure provided greater than 100 dB of isolation in passive <formula formulatype="inline"><tex Notation="TeX">${ S}$</tex></formula>-parameter measurement and suppressed in-band noise down to <formula formulatype="inline"><tex Notation="TeX">$-88~{\hbox {dBm}}$</tex> </formula> of isolation in a functional test. </para>

Fault Coverage Analysis of Peak-Detector Based BIST for RF LNAs

Analog and mixed-signal testing is becoming an important issue that affects both the time-to-market and the product cost of many SoCs. In order to provide an efficient testing method for 865---870 MHz low noise amplifiers (LNAs), which constitute a mixed-signal circuit, a novel BIST method is developed. This BIST can be easily implemented with a RF peak detector and two comparators. The circuit used in the test and the LNA are designed using 0.35 µm CMOS technology. The simulation results show higher fault coverage than that of previous test methods. A total of twenty eight short and open (catastrophic) faults and eleven variation parameters have been introduced into the LNA, giving fault coverage of 100% for catastrophic faults and parametric variation. Thus, it provides an efficient structural test, which is suitable for a production test in terms of an area overhead, a test accessibility, and test time.

Recent Advances in Analog, Mixed-Signal, and RF Testing

Due to the lack of widely applicable fault models, testing for analog, mixed-signal (AMS), and radio frequency (RF) circuits has been, and will continue to be, primarily based on checking their conformance to the specifications. However, with the higher level of integration and increased diversity of specifications for measurement, specification-based testing is becoming increasingly difficult and costly. As a result, design for testability (DfT), combined with automatic test stimuli generation, has gradually become a necessity to ensure test quality at an affordable cost. This paper provides an overview of cost-effective test techniques that either enhance circuit testability, or enable built-in self-test (BIST) for integrated AMS/RF frontends. In addition, we introduce several low-cost testing paradigms including the loopback testing, alternate testing, and digitally-assisted testing that offer the promise of significant test cost reduction with little or even no compromise in test quality. Moving forward, in addition to screening the defective parts, testing will play an increasingly important role in supporting other post-silicon quality assurance functions such as post-silicon validation, tuning, and in-field reliability of system chips.

Recent Advances in Analog, Mixed-Signal, and RF Testing

Recent Advances in Analog, Mixed-Signal, and RF Testing

Mixed-Signal Production Test: A Measurement Principle Perspective

This article, based on a tutorial the author presented at ITC 2008, is an overview and introduction to mixed-signal production test. The article focuses on the fundamental techniques and procedures in production test and explores key issues confronting the industry.

An On-Chip Analog Mixed-Signal Testing Compliant with IEEE 1149.4 Standard Using Fault Signature Characterization Technique

An on-chip analog mixed-signal testing, compliant with IEEE 1149.4 standard is presented. The testing technique is based on sinusoidal output response characterizations, yielding a complete detection of AC and DC fault signatures without a need for simulation-before-test process. The testing system is an extension of IEEE 1149.4 standard, and affords functionalities for both pre-screening on-chip and high-quality o®-chip testing. A 4th-order low pass Gm-C ¯lter was employed as a circuit-under-test, and implemented with the proposed testing approach in a physical level using 0.18-m CMOS technology, and simulated using Hspice. The maximum operating frequency of the testing circuit is 260MHz. Both catastrophic and parametric faults are potentially detectable with low performance degradation. The fault coverage of faults associated in CMOS and capacitors are relatively high at 94% and 100%, respectively.

Wafer-Level Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of ldquobig-D/small-Ardquo mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal ldquobig-D/small-Ardquo SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.