Mixed-signal ICs Research Articles

Experimental comparison of substrate noise coupling using different wafer types

Measurements of substrate coupled noise in a mixed-signal test IC are presented. This IC was manufactured with different types of wafers, and noise levels measured in heavily-doped epi wafers are about three times larger than those obtained in lightly doped ones. It is determined that, due to package parasitics, noise at the supply lines will easily be the major contributor to substrate-coupled disturbances, both at the digital and at the analog ends. Supply lines interact with the substrate mainly through the substrate contacts of both of the circuit core and the ring of pads. The measurements contribute to establishing a list of priorities in the actions to reduce the noise that reaches the analog section.

A single-chip universal cable set-top box/modem transceiver

A mixed-signal digital cable-TV transceiver IC containing two distinctly separate quadrature amplitude modulation (QAM) receivers and a single QAM modulator has been designed. An integrated 10-b analog-to-digital converter (AID) interfaces the first receiver directly to an analog signal. This receiver demodulates 4/16/32/64/128/256-QAM signals carrying the television programs or cable modem data with a variable symbol rate from 1 to 7 MBaud. A 6-b A/D is integrated to interface the second receiver to an analog signal. This receiver, used by cable operators for access control, demodulates quadrature phase shift keying (QPSK) signals with a variable symbol rate from 0.75 to 1.6 MBaud. The upstream modulator provides two-way communication required for interactive television or cable modem services. Capable of QPSK/16-QAM modulation with a variable transmission rate up to 25 Mb/s, the modulator also includes an integrated 10-b digital-to-analog converter to provide radio-frequency analog output from 0 to 65 MHz. Both receivers and the transmitter incorporate on-chip forward error correction compliant with multiple worldwide standards allowing global deployment. The carrier, phase, and timing recovery for each receiver is achieved with on-chip tracking loops. Adaptive decision feedback equalizers are incorporated to eliminate intersymbol interference. The transmitter incorporates preamble prepending and preequalization to facilitate reception. The device further integrates access control message separation, set-top box control circuitry, and a parallel microprocessor bus interface to boost system performance. The design employs a combination of semicustom and custom circuit design techniques for speed, mixed-signal performance, and layout density. Fabricated in a single poly, four-layer metal, 0.35-/spl mu/m standard CMOS process, the chip area is 64 mm/sup 2/. The device is packaged in a 256 tape ball grid array (TBGA), and dissipates 3 W at 3.3 V.

A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's

A unified modeling approach for the submicrometer MOS transistor charge/capacitance characteristics in all operation regions is presented. Development of this MOS charge model is based on the charge-density approximation to reduce the complexity of the analytical expression. To model the charge density more accurately, the conductance-degradation coefficient is determined by the derivative of drain-to-source saturation voltage with respect to gate-to-channel potential. The unified charge densities in gate, channel, and bulk regions are obtained with the assistance of the sigmoid, hyperbola, and exponential interpolation techniques. Good agreement between the measurement data and simulation results is obtained.

A video backend for multimedia TV-sets

Advanced multimedia TV-sets can handle double scan TV sources (100 Hz, progressive scan, VGA, SVGA) with resolutions up to 800/spl times/600 at 60 Hz. In addition wide screens (16:9 aspect ratio) are attractive for displaying video and PC graphics side by side. This could become a key feature for WWW-ready TV-sets. So modern TV systems face two problems: displaying different scan rates and the compatibility of aspect ratios between TV/PC sources and picture tubes. This paper describes a highly integrated display and deflection processor (DDP). The mixed signal IC contains the entire digital video component processing like chroma transient improvement (CTI), adaptive luma peaking and a nonlinear Panorama aspect ratio conversion. All deflection related signals can be adapted to different scan rates. The analog section contains all analog interface components and an ADC, to compensate long term changes of the picture tube parameters and extreme high tension effects.

Noise considerations for mixed-signal RF IC transceivers

This paper discusses design trade-offs for mixed-signal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multi-path fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit non-linearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design trade-offs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixed-signal noise coupling and to modelsubstrate noise effects are presented.

A class AB CMOS fully balanced signal generator

Mixed-signal ICs benefit greatly from processing fully balanced signals. Real-world signals are single-ended and must be converted on-chip to fully balanced signals. This article discusses a simple, accurate, low power CMOS solution to generating fully balanced signals on-chip. The design does not require common-mode feedback and provides a pin for controlling the common-mode level.

CMOS technology for mixed signal ICs

Economic and technical constraints force digital CMOS technology in a direction which is not always beneficial for analog design. The development of some analog parameters as a function of process generation is analysed. The consequences of the present developments on mixed-signal ICs are briefly discussed.

CMOS technology for mixed signal ICs

Economic and technical constraints force digital CMOS technology in a direction which is not always beneficial for analogue design. The development of some analogue parameters as a function of process generation is analysed. The consequences of the present developments on mixed-signal ICs are discussed briefly.

A design language for analog circuits

Even though analog circuit and simulation technology came first, the computer-aided design and simulation of digital circuitry is more mature. This flourishing state of affairs can be traced in part to two digital hardware description languages, VHDL and Verilog, which have fostered interchangeable designs and interoperable design and analysis tools. The same route is worth following in the analog realm. Analog circuits are increasing in number and complexity, especially in communications products and the importance of analyzing analog side-effects in high-speed digital circuits is growing rapidly. Both developments call for more highly integrated analog computer-aided design tools and hence for an analog hardware description language. Here, the author describes how interchangeable models, reliable simulation, and vendor convergence are on the horizon for analog and mixed-signal IC designers.

CMOS low-distortion high-frequency variable-gain amplifier

The overall system performance of mixed-signal CMOS IC's is largely determined by the dynamic performance of the analog front-ends. System features are, in contrast, mainly set by the digital architecture. In order to optimize the dynamic range of the system and to minimize the sensitivity to substrate noise, the analog-to-digital converter (ADC) has to be preceded by a variable-gain amplifier (VGA) and a differential circuit topology for the complete front-end to be adopted. Since most of present-day applications are based on single-sided signal source definitions, the differential-input VGA must be able to perform a single-to-differential signal conversion. This paper describes the principle and design of a differential CMOS low-distortion variable-gain amplifier for high-frequency (video) applications. Experimental results of the circuit show total harmonic distortion figures better than -60 dB and a gain accuracy of 0.05 dB over the -2 to +12 dB gain range for single-sided input signals.

Current monitoring technique for testing embeddedanalogue functions in mixed signal ICs

The authors demonstrate how M-sequences and current monitoring can be combined to produce a system level technique for testing analogue circuits, much of the test hardware being obtained from reconfigured digital system hardware.

Verification techniques for substrate coupling and their application to mixed-signal IC design

This paper presents techniques for the analysis of substrate-coupled noise in mixed-signal integrated circuits. Advantages and limitations of some commonly employed verification techniques for substrate coupling are outlined. A preprocessed boundary element method introduced in this paper utilizes precomputed z parameters to generate an analytical model for substrate impedance in a preprocessing stage. Truncated series expansions of the analytical impedance model are used to accelerate solution of the resulting boundary element equations. A methodology that applies these fast techniques to the verification of large mixed-signal circuits and results that confirm its efficiency are described. This complete methodology has been applied to the design and verification of an industrial mixed-signal video analog-to-digital converter IC for substrate noise problems.

Mixed signal test — techniques, applications and demands

The increasing importance of next generation test technology to provide high quality, low cost fault detection methodologies is becoming a big issue in the microelectronics industry. For digital ASICs, techniques such as I-ddq and built-in-self test are being introduced to supplement or in some cases replace stuck-at-testing that has been shown to be inadequate for the circuit complexities and quality levels demanded. For analogue and mixed signal ICs, a similar trend is evident. Increasing circuit complexity, higher performance and the demand for high quality levels is causing the industry to question currently used functional and specification based test programs. In addition, the escalating costs of production test equipment capable of measuring high performance device parameters is in many cases becoming a limiting factor. The authors review the current state-of-the-art in mixed signal and analogue test technology with particular reference to the consumer electronics industry. Trends in key issues such as design-for-test, fault simulation, defect detection, CAD and tester support are discussed and the possible future role of these techniques is proposed for the next generation of single chip analogue and mixed signal test systems.

Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current

In this paper we have investigated a unified and simultaneous fault detection method for mixed-signal integrated circuits. The method is based on the analysis of the power-supply current through the circuit under test. The analysis has been done paying attention to the dynamic behaviour of the power-supply current, in order to avoid measurement problems related to the large amount of quiescent current drop across many analog blocks. The analysis of the dynamic power-supply current entails certain problems related to the complexity of the measurement process, especially those due to the high speed of the current transients. These problems have been addressed by considering a design for test procedure based on the use of built-in dynamic current sensors. The goal of the design for test methodology proposed is to represent the Iddt through the mixed-signal IC under test by a digital signature. The paper presents some advantages of this approach such as a good tolerance to cross-talk noise and the need for only a conventional digital tester on the complete mixed-signal IC for fault detection. The analysis is illustrated with some test results.

Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization

An important and largely unexplored aspect of power distribution synthesis is cell customization. Through automatic cell customization, power I/O cell assignments and local substrate and power supply decoupling may be tailored to reduce deleterious noise effects on analog circuits in mixed-signal environments. Techniques for simultaneous power grid design (topology and sizing) and cell configuration/customization are described that allow designers to handle more difficult chip-level noise problems. Synthesis results on an industrial mixed-signal example demonstrate the effectiveness of this approach. >

Parametric yield prediction of complex, mixed-signal IC's

A method is presented which helps the designer predict the parametric yield of complex mixed-signal IC's in a reasonable time. It builds on previous approaches to IC yield prediction employing a Monte Carlo approach for flexibility, with behavioral simulation and response surfaces for speed. To analyze complex mixed-signal IC's, a novel feature termed the correction layer is introduced. Complex mixed-signal IC's have tests which are highly nonlinear. Consequently, it can be difficult to build accurate response surfaces whose response variables are the results of such tests. The correction layer is introduced to overcome this problem. It enables a response surface to be accurately used by the method. A commercial hard disk drive IC is analyzed as an example to show the necessity of having the correction layer in order to produce accurate parametric yield predictions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Substrate-aware mixed-signal macrocell placement in WRIGHT

We describe a set of placement algorithms for handling substrate coupled switching noise. A typical mixed-signal IC has both sensitive analog and noisy digital circuits, and the common substrate parasitically couples digital switching transients into the sensitive analog regions of the chip. To preserve the integrity of sensitive analog signals, it is thus necessary to electrically isolate the analog and digital. We argue that optimal area utilization requires such isolation be designed into the system during first-cut chip-level placement. We present algorithms that incorporate commonly used isolation techniques within an automatic placement framework. Our substrate-noise evaluation mechanism uses a simplified substrate model and simple electrical representations for the noisy digital macrocells. The digital/analog interactions determined through these models are incorporated into a simulated annealing macrocell placement framework. Automatic placement results indicate these substrate-aware algorithms allow efficient mixed-signal placement optimization. >

Reliability Issues with Mixed-Signal CMOS Technology

AbstractIn a Mixed-Signal IC, both digital and analog circuits exist on the same chip. Analog circuit blocks require technology attributes like precise device matching, low parametric drifts and low noise. These requirements raise additional reliability issues, over and above the reliability concerns associated with digital circuits. CMOS device reliability for mixed-signal technologies can be enhanced by modifying device architecture and improving gate oxide integrity. Interconnect metallurgy plays an important role in determining electromigration related contact/via resistance change which may impact matching of devices and resistor pairs. Appropriate source/drain engineering, device design and utilizing nitrided gate oxide has been shown to produce extremely stable devices. This article will cover process architecture and material issues related with device stability and interconnect metallurgy issues related with contact/via stability, especially with W-Plugs.

An 800-MHz monolithic GaAs HBT serrodyne modulator

An 800-MHz monolithic mixed-signal serrodyne modulator IC has been developed in a GaAs/AlGaAs HBT HI/sub 2/L process optimized for digital applications. This 3/spl times/2.8 mm, 2000+ transistor chip consists of a 7-b phase accumulator driving a vector modulator, implemented as a pair of balanced mixers, 5-b switched attenuators, buffer amplifiers, and central circuits. The balanced mixer's LO leakage and 3-1 products are typically 25 dB below the carrier at the nominal operating point, with all other products better than -50 dBc. Over a 32-dB control range, the 5-b switched attenuator typically achieves worst-case amplitude and phase errors of 1.5 dB and 1.5/spl deg/, respectively, from 50-250 MHz. DC-level variations versus attenuator-state limit the spurious response of an 800-MHz Composite DDS based on this serrodyne modulator to -20 dBc. Post-fabrication modeling indicates that a 5/spl deg/C thermal gradient across the IC may be responsible for this undesired dc-level variation. This first generation chip consumes 2.5 W of dc power and clocks to speeds in excess of 925 MHz. >

Measurement of digital noise in mixed-signal integrated circuits

This paper proposes a method of measuring the influence of digital noise on analog circuits using wide-band voltage comparators as noise detectors. Noise amplitude and r.m.s voltage are successfully measured by this method. A test chip is fabricated to measure the digital noise influence. From the experimental results, it is shown that the digital noise influence can be considerably reduced by using a differential configuration in analog circuits for mixed-signal IC's. The digital noise influence can be further reduced by lowering the digital supply voltage. These results show that the voltage-comparator-based measuring method is effective in measuring the influence of digital noise on analog circuits. >