Mixed-signal ICs Research Articles

Integrated AWA fitness PSO-SPICE framework for automated design and optimisation of analogue and mixed-signal ICs

Integrated AWA fitness PSO-SPICE framework for automated design and optimisation of analogue and mixed-signal ICs

Integrated AWA fitness PSO-SPICE framework for automated design and optimisation of analogue and mixed-signal ICs

Integrated AWA fitness PSO-SPICE framework for automated design and optimisation of analogue and mixed-signal ICs

When Technical Solutions are Not Enough: Using Software Concepts to Analyze Challenges at Delivery Processes Between Mixed-Signal IC Team Members

When Technical Solutions are Not Enough: Using Software Concepts to Analyze Challenges at Delivery Processes Between Mixed-Signal IC Team Members

Boosting Latent Defect Coverage in Automotive Mixed-Signal ICs Using SVM Classifiers

In industry-scale IC production, continuous improvements in processing and testing have resulted in defect test escape rates gradually reaching levels below 100 PPB for analog and mixed-signal ICs. Newer methodologies are needed to reduce these rates even further in light of the ever-tightening reliability requirements in the automotive industry while minimizing additional costs. Detecting latent defects is a major challenge today. A research experiment was conducted to assess and improve the latent defect test escape rate of industry-scale AMS testing at test time. This experiment altered the IC production process to artificially introduce latent gate oxide defects of different sizes and locations in a commercially available automotive IC in a 350high-voltage BCD process currently in production. The standard industrial test program was able to detect 58.4% of the latent defects at a yield loss of 6.2%. The latent defect detection rate has been improved to 95.5% at an additional yield loss of only 0.8% using Support Vector Machine (SVM) classifiers on the dataset of measurements resulting from the standard test program. This type of classifier is chosen for its optimal use of available data. The results show that a significant gain in coverage is possible without adding extra tests. In the experiment, testing at high temperatures (HOT) proved crucial in achieving this coverage benefit. Furthermore, while traditional tests mainly detect latent defects close to the source of transistors, the SVM approach significantly improves the detection of pinhole latent defects closer to the drain.

The History, Current Applications and Future of Integrated Circuit

Integrated circuit is a fundamental part of modern electronics, so it can be discovered in almost every electronic product. Therefore, a summary of the development of integrated circuit is very important for the professionals. The history, current applications, and challenges of integrated circuit will be discussed. In order to include all the important events of integrated circuit, in the history section, the discovery of characteristics of semiconductors, the invention of the first transistor, the first bipolar junction transistor (BJT), the first field effect transistor (FET), the first integrated circuit, and the first microprocessor will be demonstrated. Next section is about current applications by functions, including analog, digital and mixed signal IC. Finally, challenges that IC is facing right now, and prospects will be discussed. Understanding the history and current applications will help people to predict the future and find solutions of challenges.

Guest Editors’ Introduction: SBCCI 2021

The Symposium on ICs and Systems Design (SBCCI) is an international forum dedicated to ICs and systems design, test and EDA, held annually in Brazil. Over the past four decades, SBCCI has established itself as an important international forum for the presentation of research results on leading-edge aspects of ICs and systems, such as analog circuits, mixed-signal and digital ICs design, dedicated and reconfigurable architectures, EDA tools, design methods, embedded systems, SoC, and nanoarchitectures, as well as verification and test methods. This 34th edition of SBCCI was initially planned to take place in Campinas, 100 km from São Paulo. However, due to the continued health insecurity of the COVID-19 pandemic, it was transformed into a virtual event that took place from 23 to 27 August 2021.

Heterogeneous and Monolithic 3D Integration Technology for Mixed-Signal ICs

For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display, etc.) which require high-performance, small form factors, and low power consumption, heterogeneous and monolithic 3D (M3D) integration employing advanced Si CMOS technology has been intriguing. To realize the M3D-based systems, it is important to take into account the relationship between the top and bottom devices in terms of thermal budget, electrical coupling, and operability when using different materials and various processes during integration and sequential fabrication. In this paper, from this perspective, we present our recent progress of III-V devices on Si bottom devices/circuits for providing informative guidelines in RF and imaging devices. Successful fabrication of the high-performance InGaAs high electron mobility transistors (HEMTs) on the bottom ICs, with a high unity current gain cutoff frequency (fT) and unity power gain cutoff frequency (fMAX) was accomplished without substrate noise. Furthermore, the insertion of an intermediate metal plate between the top and bottom devices reduced the thermal interaction. Furthermore, the InGaAs photodetectors (PDs) were monolithically integrated on Si bottom devices without thermal damage due to low process temperature. Based on the integrated devices, we successfully evaluated the device scalability using sequential fabrication and basic readout functions of integrated circuits.

Experimental Validation of a Compact Pinhole Latent Defect Model for MOS Transistors

Currently, the semiconductor industry requires test escape levels that approach the ppb level for application domains, such as automotive. Such quality levels, however, can only be reached if latent defects are screened out, as they have become the major bottleneck in analog and mixed-signal IC testing. Latent defects can be activated using accelerated aging, but this procedure has several drawbacks. Most notably, activation can move latent defects to the product lifetime that, otherwise, would not even have expressed themselves. Therefore, methods are needed that allow the detection of these defects without using activation. Developing such methods, however, has been hampered by the lack of compact latent defect models that allow simulating circuits affected by this type of defect. This article alleviates this problem by experimentally validating a recently presented compact model for latent defects and establishing the practical range of model values that should be used in simulations. The experiments performed on a 0.35- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> technology consist of characterizing transistors containing latent defects that have been artificially introduced by etching pinholes in their gate. The measurement results corroborate that the drain current in transistors with defects increases with the area and depth of the defect, and that this behavior can be accurately modeled using an effective <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{ox}$ </tex-math></inline-formula> value.

An Interference-Tolerant Synchronization Scheme for Wireless Communication Systems Based on Direct Sequence Spread Spectrum

In this paper, an interference-tolerant three-level synchronization scheme for wireless communication systems based on Direct Sequence Spread Spectrum (DSSS) is presented. Although the proposed synchronization scheme is demonstrated in a mixed signal IC solution, it is exportable to fully digital realizations. The proposed technique synchronizes the received pseudo-random sequence (PRS) modulated signal with the receiver (RX) reference PRS by making use of its autocorrelation properties. The proposed scheme employs 3 levels that make the proposed scheme tolerant to strong in-band interferences. Experimental results for the prototype demonstrate the capabilities of the proposed approach to achieve over 50% of clock cycle tracking even in the presence of interferences with a power of 5dB higher than the desired signal power. Fabricated in a mainstream 40nm CMOS technology, the synchronization scheme employs 100MHz PRS at TX and RX; the proposed solution consumes 18.7mW power and around 0.087mm² silicon area.

Adaptive Self-Tuned Controller IC for Resonant-Based Wireless Power Transfer Transmitters

This article introduces an adaptive self-tuned controller IC for resonant wireless power transfer (RWPT) transmitters. The controller IC comprises an on-the-fly very-high-frequency tracking hardware with high resolution and an independent high-resolution digital pulsewidth modulator (PWM)-based (HR-DPWM) current programmed control. These facilitate precise frequency generation as well as adaptive tuning of the reactive components in the matching network, which translate into tight current/power regulation capabilities while retaining optimized power transfer conditions on the transmitting side. The controller IC enables to effectively disengage the power-delivery capabilities from the variations of the resonators, electrical circuits, and wireless medium. The controller core is based on a fully synthesizable digital architecture that has been realized through HDL tools, and several key building blocks have been developed and described in detail: a delay-line-based phase detector, high-resolution digital frequency synthesizer, and HR-DPWM. To fully exploit the benefits of digital electronics, reduce power consumption, and save area, the digital core of the controller has been designed completely through asynchronous architecture, eliminating the need of high-speed clock and its related hardware. The mixed-signal controller IC has been designed, implemented, and fabricated in 0.18-μm 5-V CMOS process, resulting in effective silicon area of 0.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To demonstrate the mixed-signal controller IC in closed-loop operation of a wireless power system, an experimental 20-W resonant capacitive-based WTP system has been designed and validated. The effectiveness of the controller is well demonstrated and evaluated at the MHz range up to 200 mm misalignment, meeting the strict requirements of resonant-based WPT systems.

An Efficient Sinusoid-Like Pseudo Random Sequence Modulator/Demodulator System With Reduced Adjacent Channel Leakage and High Rejection to Random and Systematic Interference

Emerging wireless communication services require the efficient use of available spectrum and improved co-existence of different standards placed in adjacent frequency bands. Co-existence with leakage from primary users in adjacent channels, which falls in the band of interest, is a primary concern for existing and emerging technologies. In this paper, a mixed signal IC technique based on direct sequence spread spectrum is proposed to improve co-existence of radar systems with commercial wireless communication systems. A sinusoid-like pseudo-random sequence is introduced to reduce leakage from radar systems into adjacent channels. The proposed approach reduces the radar signal leakage on adjacent channels by about 22dB when compared with the conventional binary pseudo-random sequence. The proposed technique randomizes narrow and wideband systematic in-band interference, after which interference power can be effectively attenuated through averaging techniques. Experimental results from a 40nm CMOS technology modulator/demodulator prototype demonstrates the feasibility of the proposed architecture. The modulator and demodulator system requires a silicon area of 0.0459mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 4.33mW in total.

Achieving high sensing in 0.5 nA for the driving pixel currents in AMOLEDs with settling time of 7 µs by a new external current sensing circuit

A new external current sensing circuit with baseline compensation for the active matrix organic light emitting diode (AMOLED) display is developed herein to achieve the sensing precision of 0.5 nA in pixel with 7 µs of settling time. Current sensing circuit incorporates a new push–pull transient current feedforward whereas the current analog to digital converter (CADC) based digital baseline current compensation incorporates an 11-bit current digital-to-analog converter, a current comparator and a digital control circuit with an 11-bit successive approximation register. The proposed integrated mixed signal IC drives a 6T1C pixel-based AMOLED panel with one horizontal time of 7.7 µs at a scan frequency of 60 Hz. The design readout chip can simultaneously sense and compensate TFT baseline current variation. The readout circuit and the baseline compensation circuit are implemented in the integrated chip with chip area of 125 μm × 46 μm and fabricated via TSMC T18 process. With the standard 3.3 V supply, experimental result shows that the overall power consumption of the chip is 988 µW watt. The minimum LSB current for the CADC is 10 nA and the maximum achievable sampling rate is 500 KS/s. The measured INL and DNL of CADC is 0.84 and 0.98 respectively. Despite of heavy data line parasitic capacitances (2.6 KΩ/20 pF) of the AMOLED display, experimental results show that the proposed circuit can sense 0.5 nA current within 7 µs of settling time. The sensing precision of 0.5 nA within 7 µs are the best among all reported literature to date whereas the current sense range (0.5–500 nA), system sampling rate (142 KS/s), INL (0.84) and DNL (0.98) of the CADC is approximately comparable among all reported.

The University of Limerick Holds Oversampled Data Converter Design Course [Chapters

The University of Limerick Holds Oversampled Data Converter Design Course The Circuits and Systems Research Group (www.csrc.ie) of the Department of Electronics and Computer Engineering, University of Limerick (UL), Ireland (www.ul.ie), held its fifth annual two-day short-course “Selected Topics in Mixed-Signal IC Design” in Limerick on 24–25 June 2019.

Failure analysis case studies of floating nets in mixed-signal IC

Two case studies concerning failure analysis on open via defects are presented in this paper. Both of them were performed on a mixed-signal product for automotive application and showed several analysis techniques used to find defective net. First example showed the use of well-known Emission Microscopy (EMMI) in combination with advanced electrical setup to highlight floating net. This case study showed the need to thoroughly interpret EMMI signatures in combination with extensive setup investigation in order to solve an analysis with a complex failure mode. Second example showed an innovative use of Dynamic Thermal Laser Stimulation to identify a floating gate.

Correction to “Evolution, Challenges and Attributes of Near Micron Sized TaN Resistors for Mixed Signal IC Applications From a Lithography Perspective” [Nov 18 460-466

The abstract in [1] is incorrect. The word “photograph” was used in error rather than the more correct, “photo.” The abstract should read: In this paper, the evolution of various lithographic processes aimed at fabricating robust tantalum nitride (TaN) resistors in GaAs-based BiFET and BiHEMT technologies are discussed in detail. Such approaches include the common image reverse photo process (via amine poisoning) using a positive tone resist, the use of a chemically amplified negative tone resist, and also straight patterning of a positive tone resist. The aforementioned approaches were found to have their own unique challenges as it applied to printing robust TaN-based resistors approaching nearly a micron in width which is needed for high density mixed signal designs. We will explore many of these challenges in detail for the various lithography schemes.

Evolution, Challenges and Attributes of Near Micron Sized TaN Resistors for Mixed Signal IC Applications From a Lithography Perspective

The abstract in [1] is incorrect. The word “photograph” was used in error rather than the more correct, “photo.” The abstract should read: In this paper, the evolution of various lithographic processes aimed at fabricating robust tantalum nitride (TaN) resistors in GaAs-based BiFET and BiHEMT technologies are discussed in detail. Such approaches include the common image reverse photo process (via amine poisoning) using a positive tone resist, the use of a chemically amplified negative tone resist, and also straight patterning of a positive tone resist. The aforementioned approaches were found to have their own unique challenges as it applied to printing robust TaN-based resistors approaching nearly a micron in width which is needed for high density mixed signal designs. We will explore many of these challenges in detail for the various lithography schemes.

Fully Integrated Digital Average Current-Mode Control Voltage Regulator Module IC

This paper introduces a fully integrated 12-to-1.xV voltage regulator module IC. A fully synthesizable digital two-loop controller has been realized through hardware description language tools. Several new IP blocks have been developed and described in detail: a window delay-line-based analog to digital converter (DL-ADC), two independent PI compensators with shared hardware for calculations, high-resolution digital pulsewidth modulation (PWM), and a programmable dead-time module. To fully exploit the benefits of digital electronics, reduce power consumption, and save area, all units of the digital controller have been designed through asynchronous architecture, eliminating the need of high-speed clock. High-performance synchronized, fixed frequency, PWM operation is enabled by a digital programmable time-base generator and system governor, which has been developed as well. In addition, to extend the capabilities of the window DL-ADC to support the full range of the load with minimal hardware penalty, adaptive reference of the current compensation is introduced. The mixed-signal IC has been fabricated on a 0.18- $\mu \text{m}$ 5-V CMOS process. It incorporates the digital controller and periphery as well as a synchronous buck power stage, including a drive circuitry that enables operation up to several megahertz from a 12-V input. The digital core has been realized by an automated synthesis process and place-and-route tools, resulting in an effective silicon area of 0.16 mm2. Experimental results of the fabricated IC operating in closed loop are provided, demonstrating the performance and benefits of the new controller for meeting the requirements of tight output voltage regulation over wide load range.

CHIMERA: A Field-Programmable Mixed-Signal IC With Time-Domain Configurable Analog Blocks

This paper presents a field-programmable mixed-signal IC named CHIMERA, for low-cost and rapid prototyping of mixed-signal systems. The proposed IC implements field-programmable analog functions with time-domain configurable analog blocks (TCABs). A single TCAB can be programmed to various analog circuits, including a time-to-digital converter, digitally-controlled oscillator, digitally-controlled delay cell, digital pulse-width modulator, and phase interpolator. The TCABs convey and process analog information using the frequency, pulse width, delay, or phase of digital pulses or pulse sequences, rather than using analog voltage or current signals for reduced susceptibility to attenuation and noise. The overall CHIMERA chip also includes arrays of configurable logic blocks (CLBs) and programmable arithmetic logic units (ALUs) for programmable digital functions. By programming the functionality of the TCAB, CLB, and ALU arrays and configuring the interconnects, the chip can implement various mixed-signal systems. A prototype IC fabricated with 65-nm CMOS technology demonstrates the versatile programmability of CHIMERA by being successfully operated as a 1-GHz phase-locked loop with a 12.3-psrms integrated jitter, as a 50-MS/s analog-to-digital converter with a 32.5-dB SNDR, and as a 1.2-to-0.7 V DC–DC converter with 95.5% efficiency.

System-Driven Circuit Design Course in Ireland [Chapters

System-Driven Circuit Design Course in Ireland A two-day short course, Short-Course on Selected Topics in Mixed-Signal IC Design, was hosted by the Circuits and Systems Research Centre (www.csrc.ie), University of Limerick, Ireland, on 7-8 September 2017. The seminar attracted 65 delegates from countries such as the Czech Republic, Spain, India, and the United Kingdom. An overview of the event is presented.

Mixed-Signal IC With Pulse Width Modulation Wireless Telemetry for Implantable Cardiac Pacemakers in 0.18-μm CMOS.

A low-power mixed-signal IC for implantable pacemakers is presented. The proposed system features three independent intracardiac signal readout channels with pulse-width-modulated outputs. Also, the proposed system is capable of measuring the amplitude and phase of the bioimpedance with pulse-width-modulated outputs for use in rate adaptive pacemakers. Moreover, a stimulation system is embedded, offering 16 different amplitudes from 1 to 7.8V. A backscattering transmitter transfers the output signals outside the body with very little power consumption. The proposed low-power mixed-signal IC is fabricated in a 0.18-μm HV CMOS process and occupies 2.38 mm2. The biopotential channels extract the heart signals with 9.2 effective number of bits and the bioimpedance channels measure the amplitude and phase of the heart impedance with 1.35 Ωrms accuracy. The complete IC consumes only 4.2μA from a 1-V power supply.