Mixed-signal Applications Research Articles

Charge pump-based PVT-resilient 45 nm CMOS dynamic comparator leveraging high speed and power efficiency

High-speed, low-power consumption, compact area, and high resolution are critical for analog /mixed signal applications. This article presents a novel design for a dynamic latch comparator that achieves exceptional speed, minimal power consumption, and a significantly reduced die area. The innovative comparator leverages a novel charge shared logic-based reset technique, which enables unparalleled speed and power efficiency. Rigorous simulations and analyses confirm that the delay time is drastically reduced compared to traditional dynamic latched comparators. The results clearly indicate that the proposed design exhibits high tolerance to PVT (process, voltage, and temperature) variations, making it highly suitable for mixed-signal applications. Designed and simulated using advanced 45 nm CMOS technology, the proposed circuit achieves an impressive delay of 18.5 ps and a remarkably low power consumption of 3.66 μW at a 1 V supply voltage and 1 GHz clock frequency.

Design and reliability assessment of an ultra-thin body electrostatically doped bipolar transistor for mixed signal applications

Shrinking of the thickness of silicon on insulator (SOI) has been proposed as a potential solution for scaling down the physical base length of symmetric lateral electrostatically doped bipolar transistors. An ultra-thin body device that utilizes the full SOI thickness has been presented and the performance of the same is investigated in detail. The device features two distinct doping techniques: work function-induced electrostatic doping (WED) and bias-induced electrostatic doping (BED). The proposed design approach leads to significant improvements in gain and cut-off frequency compared to previously reported designs. The resulting devices exhibit peak current gain β values >1100, ft>500 GHz, fmax>1300 GHz. Moreover, these improved device performance matrices get translated into better performance of universal gates with low rise and fall time of ∼1.3 ns, and improved noise margin performance in static random access memory (SRAM) device of 0.43 and 0.41 for WED and BED based devices respectively. Furthermore, the study investigates the reliability of the device concerning breakdown voltage and its response to different temperature conditions. The findings reveal a decline in the β value for WED-based devices when subjected to temperatures exceeding 340 K. In contrast, BED-based devices demonstrate a comparatively smaller variation in β at temperatures above 340 K. These results show the potential of the proposed device for mixed-signal and digital circuit applications.

Micr -Transfer Printing for Efficient 3DHI of 100-300mm Wafers and Glass Panels

This paper presents an analysis of using micro-transfer printing (MTP) for three-dimensional heterogeneous integration (3DHI) of diverse components made using 100mm, 200mm and 300mm wafers with large area glass substrates. Techniques for achieving high throughput and high wafer and substrate utilization, despite their size mis-matches, are described in detail along with MTP’s pros and cons versus alternative wafer-to-wafer and die-to-wafer 3DHI technologies. MTP, a massively parallel pick-and-place process, efficiently transfers large arrays of ultra-thin (<10 micron), small, diverse components (“x-chips”) from one or more source wafers to destination substrates. MTP enables disruptive 3DHI of compound semiconductors, including GaN, GaAs, InP, SiGe and emerging materials, silicon and passive components for wireless and optical communications, power management, sensor, photonics and other analog / mixed signal applications. Since the x-chips are ultra-thin and active side up, standard copper redistribution layer (RDL) technology may be readily used to interconnect the x-chips and destination die, resulting in very short path lengths and, hence, minimum parasitics. ASM AMICRA and X Display Company supply R&D and production MTP manufacturing systems. More than twenty MTP systems are installed worldwide at X-FAB, Micross Components, Tyndall National Institute, Teledyne, the Naval Research Laboratory, the University of Illinois Urbana Champaign, the University of Ghent / imec, UPVfab and undisclosed leading manufacturers.

On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates

Dynamic positive feedback source-coupled logic (D-PFSCL) gates are used as a low power alternative in mixed signal applications over static positive feedback source coupled logic (PFSCL) gates. In this paper, transmission gates (TG) are included in the dynamic positive-feedback source coupled logic (D-PFSCL) architecture. The proposed scheme allows implementation of logic functions which in existing schemes is restricted to NOR/OR only or three input AND/OR only realization forms. The significant reduction in the number of stages, dynamic current sources and self-timed buffer with proposed scheme leads to efficient D-PFSCL design in comparison to the existing ones. Simulations using PTM 65 nm technology node at frequency of 1 GHz are performed. A maximum improvement of 40.8%, 73% and 97% in delay, dynamic power consumption and EDP respectively is been observed for D-PFSCL exclusive-OR(XOR2) gate implemented using proposed scheme with respect to existing D-PFSCL schemes. Further, a study on the trade-off between power dissipation and frequency of operation is included for the completeness.

22 nm LDD FinFET Based Novel Mixed Signal Application: Design and Investigation

22 nm LDD FinFET Based Novel Mixed Signal Application: Design and Investigation

Homo and hetero junctionless tunnel field effect transistors for mixed signal applications: a review

Homo and hetero junctionless tunnel field effect transistors for mixed signal applications: a review

High-frequency enhancement-mode millimeterwave AlGaN/GaN HEMT with an f T/f max over 100 GHz/200 GHz* *Project supported by the National Key Research and Development Program of China (Grant No. 2020YFB1804902), the National Natural Science Foundation of China (Grant No. 61904135), the China Postdoctoral Science Foundation (Grant Nos. 2018M640957 and BX20200262), and the Natural Science Foundation of Shaanxi Province, China (Grant No.

Ultra-thin barrier (UTB) 4-nm-AlGaN/GaN normally-off high electron mobility transistors (HEMTs) having a high current gain cut-off frequency (f T) are demonstrated by the stress-engineered compressive SiN trench technology. The compressive in-situ SiN guarantees the UTB-AlGaN/GaN heterostructure can operate a high electron density of 1.27 × 1013 cm−2, a high uniform sheet resistance of 312.8 Ω/□, but a negative threshold for the short-gate devices fabricated on it. With the lateral stress-engineering by full removing in-situ SiN in the 600-nm SiN trench, the short-gated (70 nm) devices obtain a threshold of 0.2 V, achieving the devices operating at enhancement-mode (E-mode). Meanwhile, the novel device also can operate a large current of 610 mA/mm and a high transconductance of 394 mS/mm for the E-mode devices. Most of all, a high f T/f max of 128 GHz/255 GHz is obtained, which is the highest value among the reported E-mode AlGaN/GaN HEMTs. Besides, being together with the 211 GHz/346 GHz of f T/f max for the D-mode HEMTs fabricated on the same materials, this design of E/D-mode with the realization of f max over 200 GHz in this work is the first one that can be used in Q-band mixed-signal application with further optimization. And the minimized processing difference between the E- and D-mode designs the addition of the SiN trench, will promise an enormous competitive advantage in the fabricating costs.

Functional verification of a sigma-delta ADC real number model

ABSTRACT Mixed-signal applications form one of the hottest topics in the semiconductor industry. Considerable effort is required for the creation of designs that consist of both analog and digital blocks with high accuracy and performance. Therefore, mixed-signal verification can be considered as a significant matter. Former conventional verification approaches present very slow verification time, which ultimately increases time-to-market. A circuit of interest in modern systems is the sigma-delta analog-to-digital converter (ADC), which is used for encoding analog signals into digital codes, and many other applications. In this work, an effective functional verification architecture using Universal Verification Methodology (UVM) for a SystemVerilog-based sigma-delta ADC real-number model is proposed. The UVM effectiveness of the presented approach encourages the creation of a verification architecture with increased reusability and robustness, with respect to previous literature. The presented verification environment utilises constrained-random stimuli that exploit a novel sine-wave generator, analog assertions and coverage metrics for improved functional verification. Additionally, a metric for verification quality estimation is introduced for comparisons with other reference verification approaches. In all cases, the presented architecture verified the proper operation of the sigma-delta ADC with coverage of more than 98%, in accordance with the specification parameters that were used for the model.

Investigation of DC, RF and Linearity Performances of III–V Semiconductor-Based Electrically Doped TFET for Mixed Signal Applications

The aim of this paper is to bring forward a novel hetero-material electrically doped (ED) GAA TFET for high-performing and power efficient mixed signal applications. A number of low and high band gap III–V semiconductors were considered at source and drain channel regions, and their electrical characteristics were compared to identify the best alternative. To that end, DC/RF/linearity properties of AlGaSb/GaAsP, Ge/GaAs, Si/GaAs, Si/Ge, Silicon and SiGe/Si based ED GAA TFETs were analyzed. We found that the AlGaSb/GaAs-ED-TFET provides 16 $$\mu \hbox {A}$$ ON current at 25 mV/decade subthreshold swing and 1e13 $$I_{ON}/ I_{OFF}$$ ratio with exceptional analog and linearity characteristics. Also, we found that interface trap charges (ITC) in AlGaSb/GaAs-ED-TFET present negligible impact and have no effect on system performance. Further, improvisation is possible through mole fraction optimization of $$Al_{x}Ga_{1-x}Sb$$ . Finally, the mixed signal components that are widely available in system architectures are implemented using AlGaSb/GaAs-ED-TFET and their performance criteria are measured. All device simulations were performed using the TCAD Silvaco tool, and look-up based Verilog-A technique was used for circuit simulation in Cadence.

Linearity Enhancement Techniques for Operational Transconductance Amplifier: A Survey

Background: Operational Transconductance Amplifier (OTA) plays an essential role in many analog and mixed-signal applications that encourages the researchers to contribute their work to design suitable structures of OTA for their applications with acceptable performance parameters. Methods: The linearity of an OTA is one of its key performance parameters, which affects the performance of the overall system whereas the transconductance value of OTA (Gm) contributes to decide its application area. Low transconductance OTA finds its application in biomedical and neural networks while OTA with higher transconductance is suitable for wireless communication. In any system, it is desirable to obtain a linear voltage-to-current conversion, i.e., OTA, hence various linearization techniques have been reported to linearize the OTA. Results: In the last two decades, various OTA structures have been reported with linear voltage-tocurrent conversion. Some researchers used attenuation by means of different circuit approaches to linearize the OTA or some used cancellation of nonlinearity terms by using different circuit implementation techniques. Researchers used some other methods also to linearize the OTA viz source degeneration, square root technique and mobility compensation. Conclusion: The purpose of this paper is to provide a brief survey of various popular linearization techniques reported in the past.

Large-Scale Field-Programmable Analog Arrays

Large-scale field-programmable analog array (FPAA) devices could enable ubiquitous analog or mixed-signal low-power sensor to processing devices similar to the ubiquitous implementation of the existing field-programmable gate array (FPGA) devices. Design tools enable high-level synthesis to gate/transistor design targeting today's FPGA devices and the opportunity for analog or mixed-signal applications with FPAA devices. This discussion will illustrate the FPAA concepts and FPAA history. The development of FPAAs enables the development of multiple potential metrics, and these metrics illustrate future FPAA device directions. The system-on-chip (SoC) FPAA devices illustrate the IC capabilities, computation, tools, and resulting hardware infrastructure. SoC FPAA device generation has enabled analog computing with levels of abstraction for application design.

Ge–GaAs–Ge Heterojunction MOSFETs for Mixed-Signal Applications

A lattice matched heterojunction intraband tunnel (HJIBT) FET is proposed. The performance dependence of the device on conduction band (CB) discontinuity at source-channel and drain-channel interface is addressed using numerical simulation. Various mechanisms governing transport phenomena in the HJIBT FET are investigated in detail for different CB offsets (CBOs). For low gate to source voltage ( ${V}_{\text {GS}}$ ), thermionic emission is found to be the most significant transport mechanism. For moderate ${V}_{\text {GS}}$ , intraband tunneling phenomenon dominates over thermionic emission and continues to remain so. At high ${V}_{\text {GS}}$ , band-to-band tunneling occurs in HJIBT FETs. The proposed device shows improved figures of merit such as drain-induced barrier lowering (DIBL), ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) to OFF-current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ), subthreshold slope (SS), gate capacitance ( ${C}_{\text {G}}$ ), ${g}_{m}$ (transconductance), and ${f}_{T}$ (cut-off frequency), with respect to conventional MOSFET. Also, the design of a high-performance hybrid 6T-static random access memory (SRAM) is proposed.

High-sensitivity high-speed dynamic comparator with parallel input clocked switches

This paper presents a high-sensitivity high-speed dynamic voltage comparator, which is a key component for low power CMOS mixed signal applications. The proposed dynamic comparator employs ten transistors with only one cross-coupled latch to reduce the circuit complexity. The parallel clocked input switches reduce parasitic resistance in the latch ground path that results in a significant decrease in latch delay time. In addition, a symmetric, three stacked transistor, single stage architecture reduces the process variation effects, increases input sensitivity and provides more head room for low power-supply applications. The proposed design is implemented in 90 nm CMOS with 1.2 V power supply and 0.6 V reference voltage, and it provides 30 μV resolution, 105.6 μW power consumption at 2 GHz clock frequency.

Implementation of ∑Δ ADC using electrically doped III‐V ternary alloy semiconductor nano‐wire TFET

In this work, a fast and low-power sigma delta ∑ Δ analogue-to-digital converter (ADC) has been developed using a hetero-material electrically-doped nano-wire tunnel field effect transistor (HM-ED-NW-TFET) for the first time. The better gate controllability of nano-wire and immunity against process variations of electrically doped tunnel field effect transistor (TFET) enhances resolution. In this regard, the first step that has been performed is the material engineering using A l x G a 1 − x Sb / GaA s 1 − y P y , to achieve significant driving current at low subthreshold swing and high I ON / I OFF ratio. Secondly, the mole fraction is optimised to upgrade the critical analogue component – the op-amp. Also, drain under lapping is included in p-TFET to bring its characteristics as close to n-TFET. Latter, the look-up tables of the proposed device has been generated which is used to develop individual block of ∑ Δ ADC in Cadence. The blocks are well verified and integrated into final ∑ Δ ADC and its performance is evaluated. Hence, this work has explored the inherent merits of HM-ED-NW-TFET in the development of low power and fast ∑ Δ ADC by virtue of a high slew rate op-amp. Therefore, this work contributes a novel approach to explore the characteristics of emerging devices in mixed signal applications.

A Shortest Path Finding Time-Based Accelerator Core With Built-in Gravity Control and Buffer Zone for Smooth 3-D Navigation

A mixed-signal time-based 65-nm application specific integrated circuit is developed for solving shortest-path problems in 3-D. Previous path planning ASICs have been restricted to 2-D maps due to computational complexity or physical architecture limitations. Our time-based, asynchronous, one-shot architecture has been coupled with a novel dual axis interleaving strategy to solve the multidimensional shortest path problem in a simple, energy efficient manner. Additional features include circuit-based solutions for obstacle blockage avoidance and gravity. The efficacy of the proposed ASIC is evaluated on a drone navigation application, 3-D Voronoi diagrams, and a physical optics experiment. The chip is twice as energy efficient as prior 2-D work while containing $5\times $ more vertices and $7.5\times $ additional edge connections.

A custom 70-channel mixed signal ASIC for the brain-PET detectors signal readout and selection

This paper presents a 70-channel mixed signal Application Specific Integrated Circuit (ASIC) for Silicon Photo-Multipliers (SiPM) detectors, used in the axial architecture based Time of Flight (ToF) Brain-PET scanners, readout. The current pulses obtained at the output of SiPM arrays are transformed into voltages with the help of charge resistances and then passed to the low noise and high bandwidth preamplifier stages. The amplified pulses are simultaneously passed to the pulse detection modules and the low-pass Sallen-Key filtering stages. The cut-off frequency of the filtering stages is selected as 80 MHz. The denoised pulses are conveyed to the discrete times delay lines (DLs). DLs operate at a 200 MHz sampling frequency and are founded on the base of a novel parallel architecture in place of the classical bucket bridge realization. Each detection module sums up the conditioned pulses of the SiPM pair, mutually aligned 180 degrees apart, and compares its mangnitude with a Leading Edge Discriminator (LED). LEDs outputs are employed by the coincidence detection and address encoding module. DLs are parameterized in order to achieve an effective baseline of around 140 ns while properly coping with the processing delays of the pulse detection, the coincidence detection and the address encoding modules. In the case of a coincidence detection, the concerned delayed pulses are selected by piloting two multiplexers with encoded address and are passed to the post processing modules. The selection process avoids the number of false events processing. It improves the sensitivity, processing efficiency and power consumption of the system. The ASIC is implemented on the 0.35 μm BiCMOS technology. The proposed ASIC functionality is verified with post layout simulations. The typical power consumption is respectively 60.4 mW and 4.693 W for a single channel and for the whole ASIC. Results have confirmed the effectiveness of suggested solution for the SiPM detectors signals readout and selection for Brain-PET applications.

Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs

Strained silicon-on-insulator (SSOI) is a promising platform for 5G, which will require both high-performance and low-power complementary metal–oxide–semiconductor (CMOS) devices. Hence, it is important to understand the behavior of strain in SSOI at deeply scaled dimensions. We thus present a simulation study of SSOI technology, where the strain profiles of “fins” with different dimensions and layer thicknesses are analyzed. We discover, for the first time, that a buried oxide (BOX) as thin as 10–15 nm is able to effectively memorize the strain. It is also able to retain the strain under annealing up to 1000 °C, a result verified by the Raman measurements. Such a thin BOX enables a good back-gate control for dynamic threshold voltage ( ${V}_{\text{t}}$ ) tuning of SSOI transistors. The ability to have a good performance enhancement (from strain), and dynamic ${V}_{\text{t}}$ tunability (from thin BOX) makes SSOI favorable for 5G mixed-signal applications.

A CMOS temperature-independent current reference optimized for mixed-signal applications

A low-drift, high PSRR and high-accuracy CMOS temperature-independent current reference, optimized for mixed-signal applications is presented. The topology is based on bootstrap current references that present a PSRR up to 60 dB, which is required for the proposed applications since they employ circuits where high-frequency switching noise is present. The proposed approach was successfully verified in a standard CMOS 0.35 μm process. The electrical simulations and laboratory measurements confirm that for a power supply between 2.7 V and 3.6 V and temperatures between −40 °C to 80 °C range, the proposed current reference exhibits an accuracy of ±0.5% and a mean relative temperature dependency of 62.5 ppm/°C.

Impact of substrate bias and dielectrics on the performance parameters of symmetric lateral bipolar transistor on SiGe-OI for mixed signal applications

In our strive to improve upon low power high speed devices for digital and mixed signal applications, Symmetric Lateral Bipolar Transistor has come out as a promising candidate and gained importance of late. Researchers in the field have shown improved performance parameters with this novel device for digital and analog applications. We investigate for the first time the impact of substrate bias for symmetric lateral bipolar transistor on Silicon Germanium on Insulator (SiGe-OI) with varying thickness of active device area (TSiGe), thickness of BOX layer (TBox) and k-values of dielectric BOX layer for analog/mixed signal applications. We optimize our design in terms of major performance parameters like gain and fT by varying parameters like TSiGe, TBox and k-values of dielectric BOX under substrate biased condition. We were able to achieve an improvement in gain and fT (in GHz) by almost 41.7% @ IC ˜ 1 μA/μm and 1.4% respectively by increasing the k-value of BOX from 3.9 to 22 with substrate bias. We studied for the first time complementary symmetric lateral bipolar (CSLB) inverter with the introduction of high-k BOX along with substrate bias for digital applications. The inverter shows a low noise margin (NML) and a high noise margin (NMH) of 0.45 V and 0.37 V respectively when operated at 1.0 V.

Design and Implementation of SAR-ADC for Medical Electronic Applications

in today’s advance electronic and communication systems the role of high accuracy analog to digital converters are of great importance. Nowadays, a larger percentage of mixed-signal applications requires for health care systems. Also the speed of the chosen ADC design matters a lot as we are connected with the real world signals. SAR based ADC will provides us a better solution for various analog to digital systems. It is an essential device whenever data from the analog world, through sensors or transducers, should be digitally processed or when transmitting data between chips through either long-range wireless links or high-speed transmission between chips on the same printed circuit board. The paper projects up down and ring counter as a logic for successive approximation register (SAR logic for a ADC that is one of the best suited for low power. Here the resolution is of 4-bit and a power consumption of few milli watts. SAR ADC is implemented in 45 nm nano-meter scaling technology CMOS technology with a power supply of 0.5v by maintaining 4:1 w/l ratio.