Functional verification of a sigma-delta ADC real number model

Abstract

ABSTRACT Mixed-signal applications form one of the hottest topics in the semiconductor industry. Considerable effort is required for the creation of designs that consist of both analog and digital blocks with high accuracy and performance. Therefore, mixed-signal verification can be considered as a significant matter. Former conventional verification approaches present very slow verification time, which ultimately increases time-to-market. A circuit of interest in modern systems is the sigma-delta analog-to-digital converter (ADC), which is used for encoding analog signals into digital codes, and many other applications. In this work, an effective functional verification architecture using Universal Verification Methodology (UVM) for a SystemVerilog-based sigma-delta ADC real-number model is proposed. The UVM effectiveness of the presented approach encourages the creation of a verification architecture with increased reusability and robustness, with respect to previous literature. The presented verification environment utilises constrained-random stimuli that exploit a novel sine-wave generator, analog assertions and coverage metrics for improved functional verification. Additionally, a metric for verification quality estimation is introduced for comparisons with other reference verification approaches. In all cases, the presented architecture verified the proper operation of the sigma-delta ADC with coverage of more than 98%, in accordance with the specification parameters that were used for the model.