High-sensitivity high-speed dynamic comparator with parallel input clocked switches

Abstract

This paper presents a high-sensitivity high-speed dynamic voltage comparator, which is a key component for low power CMOS mixed signal applications. The proposed dynamic comparator employs ten transistors with only one cross-coupled latch to reduce the circuit complexity. The parallel clocked input switches reduce parasitic resistance in the latch ground path that results in a significant decrease in latch delay time. In addition, a symmetric, three stacked transistor, single stage architecture reduces the process variation effects, increases input sensitivity and provides more head room for low power-supply applications. The proposed design is implemented in 90 nm CMOS with 1.2 V power supply and 0.6 V reference voltage, and it provides 30 μV resolution, 105.6 μW power consumption at 2 GHz clock frequency.