A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs

Abstract

SUMMARY A novel low-power kick-back reduced comparator for usein high-speed flash analog-to-digital converters (ADC) is presented. Theproposed comparator combines cascode transistors to reduce the kick-backnoise with a built-in threshold voltage to remove the static power consump-tion of a reference. Without degrading other figures, the kick-back noiseis reduced by a factor 8, compared to a previous design without cascodetransistors. An improved calibration structure is also proposed to improvelinearity when used in an ADC. Simulated in a standard CMOS technologythe comparator consumes 106.5 μW at 1.8V power supply and 1GHz clockfrequency. key words: comparator, kick-back, calibration, low-power, flash ADC 1. Introduction Today’s high data rates necessitate the use of high-speedflash Analog-to-Digital Converters (ADC). The perfor-mance of these converters in terms of speed, power-consumption, and linearity greatly depends on the archi-tecture of the comparators used. Standard ADC designsconsist of an input-buffer/track and hold amplifier, a ref-erence ladder and a sense amplifier or S/R-type track andlatch comparator. In [1], a low power high-speed ADC de-sign was proposed, based on a switched type sense ampli-fier with built-in reference voltages. This omits the use ofa reference ladder and reduces the static power dissipation,yielding 10.6mW of power consumption at 1Gs/s and 4-bitresolution. A down-side of this design is that comparatorswitching generates considerable kick-back noise into theADC input, which necessitates the use of a low-impedancebuffer for driving the ADC, and so the overall power reduc-tion of this system is limited. Other comparators [2],[3]have been proposed with low kick-back noise. However,these approaches show a relatively high power consump-tion due to the need for a static reference ladder or due toa folded architecture. This paper presents a comparator us-ing the best of the two worlds: cascode transistors to reducethe kick-back noise while maintaining the low power con-sumption and removing the need of a static reference ladderdue to offsetting the input transistors.