A 5-bit 10GS/s 65nm flash ADC with feedthrough cancellation track-and-hold circuit

Abstract

A 10 GSamples/second (GS/s) 5-b flash analog-todigital converter (ADC) that includes a feedthrough cancellation track and hold amplifier (THA) is presented. The proposed 10 GS/s switched source follower (SSF) THA removes the input feedthrough error during the hold mode, which dramatically improves the settling behavior than previous designs. The proposed track and hold circuit achieves a total harmonic distortion (THD) of -37.3 dBc at 10 GS/s and an input frequency of 4 GHz, which is 4.5 dBc lower than the THD of traditional SSF THAs. The THA core only consumes 26 mW and this is the minimum power consumption of THA above 10 GS/s ever reported. In addition, a proposed comparator array to address the overdrive recovery issue is implemented for very high speed ADC. A reference ladder with source followers is applied to reduce the pre-amplifier feedthrough distortion by 10 times. This design is implemented in IBM 65 nm CMOS technology with 1.4 V power supply, 1.2 V peak-to-peak differential input amplitude, and 1 V peak-to-peak clock swing.