Mixed-mode Simulation Research Articles

Low-power ternary inverter using vertical tunnel field-effect transistor with pocket

ABSTRACT This paper proposes a vertical tunnel FET with pocket (VP-TFET)-based standard ternary inverter (T-inverter) model for low-power applications. Using TCAD Sentaurus tool and mixed-mode simulations, it is verified that the device can exhibit T-inverter voltage transfer characteristics (VTCs) with three steady output voltage levels when the doping length and concentration of the pocket are optimized The device’s T-inverter characteristics are achieved by employing channel-channel and source-channel tunnelling mechanisms. Current matching is crucial for n-/p–type devices to produce a steady third output voltage state. The proposed ternary inverter’s static noise margin (SNM) and static and dynamic power dissipations are computed to be 220 mV, 4.8 × 10−12 W, and 4 × 10−12 W, respectively, which assures better noise immunity and low power consumption compared to other models.

Physics-Based Artificial Neural Network Assisting in Extracting Transient Properties of Extrinsically Triggering Photoconductive Semiconductor Switches.

In this paper, a physics-based ANN assisting method for extracting transient properties of extrinsically triggering photoconductive semiconductor switches (ET-PCSSs) is proposed. It exploits the nonlinear mapping of ANN between transient current (input) and doping concentration (output). According to the basic laws of photoelectric device operating, two types of ANN models are constructed by gaussian and polynomial fitting. The mean absolute error (MAE) of forecasting transient photocurrent can be less than 10 A under low triggering optical powers, which verifies the feasibility of ANN assisting TCAD applied to PCSSs. The results are comparable to computation by Mixed-Mode simulation, yet even thousands of seconds of CPU runtime cost are saved in every period. To improve the robustness of the Poly-ANN predictor, Bayesian optimization (BO) is implemented for minimizing the curl deviation of photocurrent-time curves.

Study of performance evaluation of various characteristics of a single phase full bridge inverter circuit using surrounded channel junctionless field effect transistor

This paper reports the characteristics study of a single phase full bridge power electronic inverter circuit with a new type of technology namely surrounded channel junctionless field effect transistor (SCJLFET) as a switch. The inverter circuit has been designed using mixed mode simulation platform of TCAD device simulator. The transient characteristics for various temperatures and work functions have been analysed. In the steady state analysis the output current and voltage variation with input voltage with various temperatures and work functions have been studied. The power factor variations with gate oxide thickness and dielectric constant of gate dielectric. The simulation and designing process along with pros and cons have been characterized. The SCJLFET would be one of the strongest participants for advanced power electronics technology as a switches, with various virtues of high-speed operation, low power consumption and low budget process integration. It has also been found that single phase full bridge inverter is giving best results when made using SCJLFET.

Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors.

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat's impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs.

Design of polarity hardening SRAM for mitigating single event multiple node upsets

With technology scaling down, the charge sharing among multiple nodes has becoming significant, making Single Event Multiple Node Upsets (SEMNUs) has become one of the major concern in memory cell designs. In this paper, a design of polarity hardening memory cell (PH_14T) is proposed for mitigating Single Event Multiple Node Upsets (SEMNUs). Through the 3D TCAD mixed-mode simulation established that the high robustness against SEU and SEMNUs of the PH_14T cell. Additionally, Cadence Spectre simulation results demonstrated that the proposed PH_14T cell has smaller write access time, lower power consumption, and highest critical charge compared to radiation-hardened cells. Monte Carlo simulation further confirmed the high radiation tolerance and high reliability of the proposed cell against SNU and DNU.

Strain-rate dependent mixed-mode traction laws for glass fiber-epoxy interphase using molecular dynamics simulations

In this paper, we establish a methodology to predict strain rate-dependent mixed-mode traction-separation responses (i.e., traction laws) for glass-epoxy composite interphase using molecular dynamics (MD) simulations. Glass-epoxy interphases with monolayer glycidoxypropyltrimethoxy silane are prepared by varying silane number density from 0.0 nm−2 to 3.9 nm−2 following the epoxy-amine diffusion and curing reactions. To established the effects of strain rate and mode-mixity on the interphase traction laws, the nano-meter size interphase domain is loaded in various mode-mixity (θ=0°(Mode−II),15°,30°,45°,60°,and90°(Mode−I)) with full range of strain rates from quasit-static to high strain rate (∼1e16/s) where a theoretical plateau strength limit is predicted. Following our previous work on Mode-I [Chowdhury et al., Composites Part B 237 (2022) 109877], mathematical model is developed for Mode-II as function of strain rate for different interphase structures (i.e., silane number density). The continuum equivalent bi-linear cohesive traction law is developed using the MD results to determine the mode-mixity quadratic functions and associated exponents for peak tractions, energy absorption, crack initiation and crack opening displacement from the mixed-mode simulations data. The MD predicted traction laws can be used to model interphase in micromechanics finite element analysis to bridge the length scale for the prediction of fiber-matrix debonding in composites.

Logic-in-memory application of silicon nanotube-based FBFET with core-source architecture

The performance of a silicon nanotube-based feedback field-effect transistor (SiNT FBFET) with a core-source architecture has been explored in this work for the use in logic-in-memory (LIM) applications. Both n-channel and p-channel FETs with extremely symmetric transfer characteristics and a high ON/OFF current ratio of 109 are implemented in a single structure using the core and outer gates. SiNT FBFET exhibits significant data retention attributes during memory operations for up to 103 s. The SiNT FBFET-based inverter circuit retains output logic states of “1” and “0” for 1.705 s and 1.948 s, respectively, at megahertz operating frequency without standby power consumption. Additionally, SiNT FBFET has also been used to build ternary NAND/NOR logic gates with memory functionality. Numerical mixed-mode simulations of the circuits have been carried out using the commercially available Synopsys “Sentaurus” TCAD tool for examining the performance and memory characteristics of SiNT FBFETs. This study demonstrates the possible use of SiNT FBFET in multivalued logic systems and the development of next-generation memory devices.

Mole Fraction and Device Reliability Analysis of Vertical-Tunneling-Attributed Dual-Material Double-Gate Heterojunction-TFET with Si0.7Ge0.3 Source Region at Device and Circuit Level

This paper puts forward a new vertical-tunneling-attributed dual-material double-gate heterojunction-TFET (VTDMDG-HTFET). The device structure of VTDMDG-HTFET includes Si[Formula: see text]Ge[Formula: see text] material for the designing of source region. The mechanism of vertical tunneling in VTDMDG-HTFET provides superior electric field at tunneling interface and leads to improved transfer characteristics. VTDMDG-HTFET also includes metal gate work-function engineering approach to facilitate high ON-current and small OFF-current. Application of high-[Formula: see text] dielectric material HfO2 in the form of gate oxide enhances the capacitive-coupling at channel-source interface. Moreover, the work includes the comparison of proposed VTDMDG-HTFET with the conventional vertical-tunneling based dual-material double-gate-TFET (VTDMDG-TFET). It has been observed from the simulation results that SiGe source-based VTDMDG-HTFET offers better DC characteristics in terms of superior ON-current, smaller OFF-current, steeper subthreshold-slope, lower threshold voltage, higher transconductance along with smaller drain-induced barrier-lowering (DIBL) effects as compared to its counterpart silicon-source-based VTDMDG-TFET. In this work, reliability of VTDMDG-HTFET has also been examined and compared with VTDMDG-TFET in terms of temperature sensitivity and effect of different interface trap charges. The device simulation and investigations have been carried out using technology computer aided design (TCAD) tool. Moreover, device circuit mixed-mode simulation analysis is carried out for conventional and proposed device based resistive load inverters. A comparison is performed between both the inverters in terms of prorogation delay and switching threshold voltages. Further, the mixed mode simulation analysis is also performed for the proposed device based inverter under the influence of different interface trap charges (ITCs). Study shows that reliability performance of the proposed device is better as compared to its counterpart conventional device. Hence, vertical tunneling and SiGe source-based VTDMDG-HTFET can be a better choice for various applications such as analog/RF, analog and digital electronic circuits, energy harvesting, gas-sensing and memory devices.

A Novel Enhancement-Mode Gallium Nitride p-Channel Metal Insulator Semiconductor Field-Effect Transistor with a Buried Back Gate for Gallium Nitride Single-Chip Complementary Logic Circuits

In this work, a novel enhancement-mode GaN p-MISFET with a buried back gate (BBG) is proposed to improve the gate-to-channel modulation capability of a high drain current. By using the p-GaN/AlN/AlGaN/AlN double heterostructure, the buried 2DEG channel is tailored and connected to the top metal gate, which acts as a local back gate. Benefiting from the dual-gate structure (i.e., top metal gate and 2DEG BBG), the drain current of the p-MISFET is significantly improved from −2.1 (in the conv. device) to −9.1 mA/mm (in the BBG device). Moreover, the dual-gate design also bodes well for the gate to p-channel control; the subthreshold slope (SS) is substantially reduced from 148 to ~60 mV/dec, and such a low SS can be sustained for more than 3 decades. The back gate effect and the inherent hole compensation mechanism of the dual-gate structure are thoroughly studied by TCAD simulation, revealing their profound impact on enhancing the subthreshold and on-state characteristics in the BBG p-MISFET. Furthermore, the decent device performance of the proposed BBG p-MISFET is projected to the complementary logic inverters by mixed-mode simulation, showcasing excellent voltage transfer characteristics (VTCs) and dynamic switching behavior. The proposed BBG p-MISFET is promising for developing GaN-on-Si monolithically integrated complementary logic and power devices for high efficiency and compact GaN power IC.

A Two-Dimensional Computer-Aided Design Study of Unclamped Inductive Switching in an Improved 4H-SiC VDMOSFET.

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (Ron,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements.

A dynamic description of the smoothing gradient damage model for quasi-brittle failure

Quasi-static simulations are of limited interest because cracks, if they are not severely constrained, propagate dynamically. When natural disasters such as earthquakes or explosions happen, structures made of quasi-brittle or brittle materials can suffer from failures activated by, for instance, loading at a high rate. Dynamic fractures, especially dynamic crack branching, are often observed during those events. We present in this paper, for the first time, a dynamic description of the smoothing gradient-enhanced damage model towards the simulation of quasi-brittle failure localization under time-dependent loading conditions. We introduce two efficient rate-dependent damage laws and various equivalent strain formulations to analyze the complicated stress states and inertia effects of dynamic regime, enhancing the capability of the adopted approach in modeling dynamic fracture and branching. The study is carried out using low-order finite elements, and the merits of the developed approach are examined through our numerical experiments, including mixed-mode fracture and dynamic crack branching simulations.

Design of Binary and Ternary Logic Inverters Based on Silicon Feedback FETs Using TCAD Simulator

A feedback field effect transistor (FBFET) with p-n-p-n structure benefits from a positive feedback mechanism. In this structure, the accumulated charges in its potential well and limitation of carrier flow by its internal potential barrier lead to superior electrical properties such as lower subthreshold swing (SS) and higher I ON / I OFF ratio in comparison with FinFET. Thus, FBFET is a promising alternative for digital applications such as logic inverters. In this paper, binary and ternary logic inverters are designed by using FBFETs with 40 nm channel length. The doping profile in the device plays an essential role and specifies the binary or ternary operation of the inverter. The inverter is analyzed by using a TCAD mixed-mode simulator. The results indicate the high value of 1010 for I ON / I OFF ratio with an extremely low SS (1 mV/decade). The voltage transfer characteristics of the inverter and its dependence on doping levels have been investigated. Also, the electrical properties of this inverter are compared with previous inverter counterparts.

Influence of avalanche transistor switching mode on waveform characteristics of solid-state pulse source.

The design of the Marx circuit based on avalanche transistors (ATs) is one of the effective techniques for developing solid-state pulse sources to generate nanosecond pulses. However, the influence of the avalanche transistor as a switching device on the output pulse characteristics is still unclear. In this study, investigating the switching mechanism of the AT with a mixed-mode simulation of the semiconductor device has been accomplished. An experiment has checked the simulation model's transient switching characteristics. The switching mechanisms of ATs in the Marx circuit were divided into base triggering mode (BTM) and voltage ramp mode (VRM). This paper proposes a modified circuit for adjusting the output pulse parameters of solid-state pulse sources. The results show that to satisfy the simulation accuracy, the width parameter of the AT model in the BTM must be 100μm, much less than the actual physical size. Because of the higher electric field when the initial impact ionization occurs, the AT operates at a higher switching speed in the VRM than in the BTM. In addition, since the carriers of initial impact ionization locate at the p-n0 interface or the n0-n+ interface, the AT switching process will oscillate in the VRM. All ATs in the modified Marx circuit switch to operate in the BTM. The leading edge of the output pulse increases from 275 to 1125ps, and the pulse trailing oscillation has disappeared. The research results provide an important technical means for optimizing the output waveform of solid-state pulse sources.

Investigation of switching and inverter characteristics of Recessed-Source/Drain (Re–S/D) Silicon-on-Insulator (SOI) Feedback Field Effect Transistor (FBFET)

In this paper, the switching and inverter characteristics of Recessed-Source/Drain (Re–S/D) Silicon-on-Insulator (SOI) Feedback Field Effect Transistor (FBFET) are presented using a TCAD mixed-mode simulator. FBFETs have recently acquired popularity as alternative steep-switching devices. It has a very steep subthreshold slope (SS) and high ON current (ION). The current in the device is caused by the movement of electrons and holes which creates positive feedback. To improve the device characteristics in SOI FBFET, a Re–S/D technique is incorporated by extending the source and drain regions into the buried oxide (BOX). An improvement in the IONis observed with reduced hysteresis (memory window) in a Re–S/D SOI FBFET compared to conventional SOI FBFETs which is very useful in logic applications. A complementary inverter implemented using n-type and p-type Re–S/D SOI FBFETs is found to have improved voltage transfer characteristics (VTC) and transient response levels than those of SOI FBFET-based inverters. The high logic level is improved to 0.882V from 0.85V and the low logic level is improved to 0.1V from 0.15V in both VTC and transient response of SOI FBFET inverter at a Re–S/D thickness of 50 nm. Hence, a Re–S/D technique is very useful for both improvements in ION and tackling the problem of clear ON/OFF states in FBFET devices. Further, the three-stage Re–S/D SOI FBFET inverter-based ring-oscillator is implemented, and found that the frequency (fo) and propagation delay (tp) are improved with increased Re–S/D thickness.

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors.

Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated. Cell reliability is closely related to device malfunction. Hence, in this study, we propose a 1T DRAM consisting of an FBFET with a p+-n-p-n+ silicon nanowire and investigate the memory operation and disturbance in a 3 × 3 array structure through mixed-mode simulations. The 1T DRAM exhibits a write speed of 2.5 ns, a sense margin of 90 μA/μm, and a retention time of approximately 1 s. Moreover, the energy consumption is 5.0 × 10-15 J/bit for the write '1' operation and 0 J/bit for the hold operation. Furthermore, the 1T DRAM shows nondestructive read characteristics, reliable 3 × 3 array operation without any write disturbance, and feasibility in a massive array with an access time of a few nanoseconds.

Determining the Zero-Temperature-Coefficient Point From Device Simulation to Circuit for Improving Temperature Variation Immunity

Thermal issue emerges as one of the critical reliability concerns in integrated circuit design, especially for advanced technology. To improve the temperature immunity and reduce the thermal-related timing guard bands in digital circuits, in this work, we offer a new insight into the zero-temperature-coefficient (ZTC) based design strategy featuring minimizing the temperature-induced delay variation. An effective current-based method to facilitate the ZTC point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> ) determination for standard cells is developed, which is demonstrated on advanced gate-all-around (GAA) nanosheet (NS) FETs from 300 to 425 K using the calibrated TCAD simulation. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> dependencies on the signal input slew rate, output capacitance, and self-heating effects (SHEs) are further investigated from the perspective of the effective current by tracing the voltage trajectory. The mixed-mode TCAD simulation results show that the frequency variation of ring oscillator (RO) reduces nearly ten times when operating near <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> and great power-performance trade-offs can also be achieved. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> determination for standard cells combined with the compensation effect among different standard cells benefits selecting the optimal zero-temperature-delay (ZTD) point in the target path, thereby helping to implement a robust digital design against temperature variation.

Capacitor-Less Low-Power Neuron Circuit with Multi-Gate Feedback Field Effect Transistor

Recently, research on artificial neuron circuits imitating biological systems has been actively studied. The neuron circuit can implement an artificial neural network (ANN) capable of low-power parallel processing by configuring a biological neural network system in hardware. Conventional CMOS analog neuron circuits require many MOSFETs and membrane capacitors. Additionally, it has low energy efficiency in the first inverter stage connected to the capacitor. In this paper, we propose a low-power neuron circuit with a multi-gate feedback field effect transistor (FBFET) that can perform integration without a capacitor to solve the problem of an analog neuron circuit. The multi-gate FBFET has a low off-current due to its low operating voltage and excellent sub-threshold characteristics. We replace the n-channel MOSFET of the inverter with FBFET to suppress leakage current. FBFET devices and neuron circuits were analyzed using TACD and SPICE mixed-mode simulation. As a result, we found that the neuron circuit with multi-gate FBFET has a low subthreshold slope and can completely suppress energy consumption. We also verified the temporal and spatial integration of neuron circuits.

Virtual element method for mixed-mode cohesive fracture simulation with element split and domain integral

We present a computational framework for mixed-mode cohesive fracture simulation based on the virtual element method (VEM). To represent an arbitrary crack path, the element splitting scheme is developed on a polygonal mesh to capitalize its flexibility in element shape. For the accurate evaluation of a crack-tip stress field and crack propagation direction, the virtual grid-based stress recovery scheme is tailored for VEM in conjunction with the maximum strain energy release rate criterion. The mixed-mode fracture examples are illustrated to validate the accuracy and robustness of the proposed computational scheme. Numerical results demonstrate that the domain integral method with the stress recovery scheme captures an accurate crack path without oscillation under the biaxial tensile stress state. Furthermore, the computed cracks using the element splitting scheme show that smooth and curved patterns on polygonal elements are in good agreement with the experimental results.

3D-TCAD benchmark of two-gate dual-doped Reconfigurable FETs on FDSOI28 technology

Through 3D-TCAD simulations this work aims to demonstrate the benefits of Reconfigurable FETs based on dual doping with respect to the Schottky junctions counterparts using the 28 nm FDSOI platform. These devices feature both N and P dopant species at source and drain to allow for electron and hole symmetrical currents instead of using mid-gap metallic regions. Quasi-static results reveals much larger currents thanks to the enhanced carrier injection with analogous capacitances, leading to faster logic circuits in mixed-mode simulations. Dynamic results also show lower energy-delay products making these devices more efficient and appealing to implement reprogrammable logic.

Mixed-mode fatigue crack propagation simulation by means of [formula omitted] and walker models of the structural steel S355

In this paper, a numerical simulation method of mixed-mode fatigue crack propagation was explored using the extended finite element method (XFEM) and the Virtual Crack Closure Technique (VCCT). Both 2D and 3D numerical models were selected to simulate the fatigue crack propagation of steel specimens. Two coefficients were proposed to calculate the equivalent energy release rate (Geq) for a better simulation of the mixed-mode fatigue crack propagation of S355 steel. The Walker equation and the calculation formula of Geq were realized by a user-defined subroutine. A set of optimal correction coefficients of mode II energy release rate (GII) and mode III energy release rate (GIII) were quantitatively comparing the simulation results and test data. The results will contribute to fatigue crack propagation prediction of steel structures in the civil engineering field.