Transistor Mismatch Research Articles

Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM

A modified decoupled sense amplifier (MDSA) and modified decoupled sense amplifier with NMOS foot-switch is proposed for improved sensing in differential SRAM for low-voltage operation at the 22-nm technology node. The MDSA and MDSANF both offer notable improvements to read delay over conventional voltage and current sense amplifiers. At an operating voltage of 0.8 V, the MDSA exhibited a reduced delay of 28.6%, 41.79%, 37.74%, and 30.94% compared to modified clamped sense amplifier (MCSA), double tail sense amplifier (DTSA), modified hybrid sense amplifier (MHSA), and conventional latch-type sense amplifier (LSA), respectively. Similarly, the MDSANF demonstrated a delay reduction of 26.13%, 39.78%, 35.58%, and 28.55% over MCSA, DTSA, MHSA, and LSA, respectively. To validate the performance, the MDSA and MDSANF are evaluated using the variation in delay and power consumption across various supply voltages, process corners, input differential bit line voltage (ΔV BL ), bit line capacitance (C BL ), and the sizing of decoupling transistors. Monte Carlo simulations were conducted to analyse the impact of voltage threshold variations on transistor mismatch which leads to an increased occurrence of read failures and a decline in SRAM yield. The performance analysis of various voltage and current sense amplifiers is presented along with MDSA and MDSANF. Area consideration for selection of sensing scheme is important and as such layout of MDSA and MDSANF was performed conforming to the design rules and estimated area for MDSA is 0.297 μm 2 whereas MDSANF occupies 0.5192 μm 2 .

A Current Reference With Multiple Nonlinear Current Mirrors to Reduce Noise, Mismatch, and Impact of Supply Voltage Variation

This paper presents two improved concepts for self-biased current references. The first approach consists of a current loop with not only one linear and one nonlinear current mirror, but with two stacked complementary nonlinear current mirrors. By this, noise, mismatch and impact of supply voltage variation can be reduced by up to a factor of 2 (6 dB). The second approach is designed and manufactured for test purposes in a 0.18 μ m 3.3 V standard CMOS technology and consists of multiple nonlinear current mirrors connected in series within a loop. An evaluation of 20 die-to-die prototypes of this novel current reference concept shows that current noise, local transistor mismatch and impact of supply voltage variation can be reduced by up to 6 dB with two nonlinear current mirrors connected in series and by up to another 3 dB with each additional nonlinear current mirror. Furthermore, the suppression of global process tolerances can be significantly improved in both approaches by using nonlinear current mirrors, each consisting of a different type of transistor with uncorrelated oxide thickness statistics between these different transistor types. A Monte Carlo lot-to-lot simulation in the 0.18 μ m CMOS technology with a sample size of 1000 shows that the expected worst-case tolerance (± 3σ/mean) of those current references should be smaller than ± %.

Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes

Today it is important to manufacture high quality integrated circuits which are insensitive to device mismatches. This paper presents an analysis of MOSFET transistors mismatches effect on the performance of UWB receiver front-end which constitute the most important part of Wireless Body Area Network sensor node. The receiver is based on Balun LNA with 25% fully differential double-balanced passive mixer. A PMOS and NMOS transistors mismatch models were proposed to determine LNA output offset voltage and mixer offset current respectively. The analysis result suggests that, to minimize NMOS current mismatch, and thus reducing second-order inter modulation distortion, the overdrive voltage must be maximized. A Monte Carlo and harmonic balance simulations were performed using 0.18µm CMOS process to evaluate the impact of mismatch as well as Vth mismatch on the receiver gain and IIP2. Simulation results show that IIP2 of the receiver is less sensitive to mixer NMOS mismatch but receiver gain is more sensitive. The receiver IIP2 confidence interval in case of NMOS mismatch is [24.674, 24.77]dBm and in case of NMOS Vth mismatch is [24.659, 24.857]dBm. This show the robustness of the proposed UWB receiver front end. Therefore the proposed circuit meets the requirement of UWB system perfectly which make it suitable for WBAN applications.

An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset

Sense amplifiers (SA) are facing increasing offset problems and amplifying problems due to mismatch of transistors and variations. This paper presents a structure that cancels the offset which is based on the delay and offset relation. The proposed structure can measure the delay of an SA due to its own offset voltage, and convert it into the length of a correction signal. The correction signal discharges the input of the SA, which reduces the voltage of the input to cancel the offset of the SA. The proposed technique can be applied to both the conventional latch-type SA (CLSA) and the current-latched SA with an NMOS footswitch (CSANF). The schematic simulations based on the 28 nm complementary metal-oxide semiconductor process show that the proposed technique can achieve a more centralized offset distribution than the CLSA and the CSANF. Moreover, the offset voltage of the two types SA can be reduced by 71.42% and 65.95%, respectively.

Quantification of Substrate Current Caused by an Individual Trap at Different Locations and Energies, Prevailing on Si/SiO₂ Interface or Si Substrate of n-MOSFETs

Traps on Si/SiO₂ interface or Si substrate are a big source of variability that cause the mismatch of transistors’ performance and leads to failure. To have a comprehensive view of individual traps, causing random fluctuations, variable trap locations are considered on Si/SiO₂ interface and Si substrate. Each trap location is filled with a trap alternatively and simulated via Sentaurus TCAD at five different energy levels (0.35-0.55 eV with a difference of 0.05 eV). The electron charge pumping cycle is recorded to understand each trap

Novel Resistorless, Cascadable Current-Mode Precision Rectifier Using CFDITA

The paper introduces a new circuit structure of precision full-wave rectifier, without the requirement of any diode(s) and passive component(s), which operates in current mode. The proposed structure of the rectifier employs a single current follower differential input transconductance amplifier and two MOS transistors only. The use of the least number of active components makes the circuit structure simple and favorable to the contemporary integration technology. The proposed rectifier has wider input current dynamic range (±1.6 mA), lower current offset (84 pA), and can operate up to 30 MHz frequency. Additionally, the circuit is easily cascadable, temperature insensitive, and less affected by process variation, MOS transistors mismatch, and supply voltage variation. The rectifier circuit is verified through 0.18 µm gpdk technology-based post-layout simulation results using the cadence Virtuoso tool. The rectification accuracy is examined through the parameters, such as average value ratio and root mean square error. The proposed rectifier’s layout measures 31.95 µm × 31.35 µm in size.

An electronically tunable CMOS implementation of capacitance multiplier employing CCCDTA

In this work, a new design for the grounded capacitance multiplier is proposed. The proposed circuit is based on the analog building block of Current Controlled Current Differencing Transconductance Amplifier (CCCDTA) which allows the multiplier structure to work in the current mode. CMOS realization of the proposed structure is implemented with 0.18 µm CMOS technology for the grounded adjustable capacitor multiplier. Multiplication factor adjustability is realized by the bias current of Current Difference Unit (CDU) of CCCDTA. All simulations performed at post-layout level (209 µm × 67 µm) in Cadence environment by taking into account Monte-Carlo runs comprising process variations and transistor mismatches. Also, performance of the proposed multiplier structure is validated by using commercial elements such as AD844 and LM1370. In comparison to the counterparts in the literature, the proposed architecture including only single active element gives promising results under different operating conditions for a wide range of frequency.

Spiking Cochlea With System-Level Local Automatic Gain Control

Including local automatic gain control (AGC) circuitry into a silicon cochlea design has been challenging because of transistor mismatch and model complexity. To address this, we present an alternative system-level algorithm that implements channel-specific AGC in a silicon spiking cochlea by measuring the output spike activity of individual channels. The bandpass filter gain of a channel is adapted dynamically to the input amplitude so that the average output spike rate stays within a defined range. Because this AGC mechanism only needs counting and adding operations, it can be implemented at low hardware cost in a future design. We evaluate the impact of the local AGC algorithm on a classification task where the input signal varies over 32dB input range. Two classifier types receiving cochlea spike features were tested on a speech versus noise classification task. The logistic regression classifier achieves an average of 6% improvement and 40.8% relative improvement in accuracy when the AGC is enabled. The deep neural network classifier shows a similar improvement for the AGC case and achieves a higher mean accuracy of 96% compared to the best accuracy of 91% from the logistic regression classifier.

Redundant Crossfire: A Technique to Achieve Super-Resolution in Neurostimulator Design by Exploiting Transistor Mismatch

A high-resolution neurostimulator is the essential component of many bidirectional neural interfaces. In practice, the effective resolution of fully integrated neurostimulator designs is often hindered by the transistor mismatch, especially in submicrometer CMOS processes. In this article, we present a new circuit technique called redundant crossfire (RXF) to address this challenge. It is derived from our redundant sensing (RS) framework, which aims at engineering information redundancy into the system architecture to enhance its effective resolution. RXF involves combining (i.e., crossfiring) the outputs of two or more current drivers to form a redundant structure that, when properly configured, can produce accurate current pulses with an effective super-resolution beyond the limitation commonly permitted by the physical constraints. Unlike any previous works, the proposed technique achieves high-accuracy by directly exploiting the random transistor mismatch with an excessively large mismatch ratio of 10%–20%. The effectiveness of RXF is verified through both Monte Carlo simulations and measurement results of a fully integrated neurostimulator chip. Equipped with a 5-bit current digital-to-analog converter (IDAC) and two 4-bit current multipliers, the stimulator achieves an effective resolution of 9.75 bits in a 1.1-mA full range. An application of the fabricated chip is to deliver neuro-feedback to a human amputee through peripheral nerves where the amplitude of stimulation pulses is accurately controlled to encode the tactile response’s intensity.

Implementation and analysis of tunable fractional-order band-pass filter of order 2α

This paper proposes a new design of a 2α-order fractional-order band-pass filter with tunability feature. The proposed filter is approximated with the Continued Fraction Expansion and Matsuda second-order approximations. The realized filter transfer function is based on the Inverse Follow the Leader Feedback configuration, with Operational Transconductance Amplifiers as active elements. As a result, the order of the proposed filter can be adjusted by changing a single parameter, which is the bias current Ibias. A comparison with the previous works is performed, showing the advantage of the electronic tuning feature using one bias current value in the proposed filter. Sensitivity analysis is conducted to investigate the effect of circuit parameters variation, such as capacitance and gain factors. Stability analysis is performed by studying the poles’ location and movement versus the filter parameters. Besides, the effect of transistor mismatch is evaluated using Monte Carlo analysis. Matlab and Cadence software, with UMC technology of 0.13 μm CMOS, are used for verifying the proposed implementation.

A current-mode system to self-measure temperature on implantable optoelectronics

BackgroundOne of the major concerns in implantable optoelectronics is the heat generated by emitters such as light emitting diodes (LEDs). Such devices typically produce more heat than light, whereas medical regulations state that the surface temperature change of medical implants must stay below + 2 °C. The LED’s reverse current can be employed as a temperature-sensitive parameter to measure the temperature change at the implant’s surface, and thus, monitor temperature rises. The main challenge in this approach is to bias the LED with a robust voltage since the reverse current is strongly and nonlinearly sensitive to the bias voltage.MethodsTo overcome this challenge, we have developed an area-efficient LED-based temperature sensor using the LED as its own sensor and a CMOS electronic circuit interface to ensure stable bias and current measurement. The circuit utilizes a second-generation current conveyor (CCII) configuration to achieve this and has been implemented in 0.35 μm CMOS technology.ResultsThe developed circuits have been experimentally characterized, and the temperature-sensing functionality has been tested by interfacing different mini-LEDs in saline models of tissue prior to in vivo operation. The experimental results show the functionality of the CMOS electronics and the efficiency of the CCII-based technique with an operational frequency up to 130 kHz in achieving a resolution of 0.2 °C for the surface temperature up to + 45 °C.ConclusionsWe developed a robust CMOS current-mode sensor interface which has a reliable CCII to accurately convey the LED’s reverse current. It is low power and robust against power supply ripple and transistor mismatch which makes it reliable for sensor interface. The achieved results from the circuit characterization and in vivo experiments show the feasibility of the whole sensor interface in monitoring the tissue surface temperature in optogenetics.

Analog 8-point DFT processor with low-power consumption and high-speed for interference mitigation in GPS receivers

In this paper, the CMOS current mirror-based analog 8-point discrete Fourier transform (DFT) circuit with low power consumption, high accuracy and high speed is presented to mitigate the interferences in Global Positioning System (GPS) receiver. As a hardware method, an anti-jamming block is placed in GPS prior to automatic gain control. The main core of this block is the DFT processor. In comparison to the conventional digital and analog methods, the techniques and structure used to implement 8-point DFT have higher speed and lower power consumption with a fewer number of transistors. Considering the properties of current-mode analog circuits at two levels of algorithm and circuit, two new structures along with some improvement techniques are presented in this paper. Compared to butterfly model algorithm, the proposed designs are superior in all parameters including the number of transistors, power consumption, propagation delay, speed, accuracy and the amount of sensitivity to transistors mismatch. The simulation results in complex differential mode show that, the proposed 8-point DFT is able to reach a response rate of 3.98 ns, power consumption of 37.57 mW and error mean about 1% in a wide range of input current changes between 0 and 100 µA.

A novel VLSI design of radix-4 DFT in current mode

ABSTRACTDiscrete-time Fourier transform (DFT) is viewed as an important tool in discrete time signal processing. Applications in wireless communication such as OFDM uses DFT/IDFT in its receiver and transmitter. For small battery powered wireless devices, discrete time analogue DFT can be very useful as a low-energy front-end. The quest for a reduction in the effect due to the mismatch of transistors lead to higher radix structure. It becomes very challenging for the designer to build an analogue circuit for implementation of DFT with radix sizes 4, 8, and so on. This is mainly because of hand calculation of circuit-level equations from butterfly algorithm becomes a long process. Thus, a design methodology becomes a necessary option in this regard. Here an algorithm is proposed for the generation of circuit-level equations leading to signal routing table for the circuit of basic radix-4 FFT. Following that algorithm, a current mode all analogue circuit with cascode current mirror is proposed. Simulations are carried out in SPICE using BSIM4 65 nm CMOS process. A mismatch noise model is also made to show the reduction in error with higher radix structure. The non-ideal effects due to mismatch in Vth are analysed through Monte-Carlo simulation.

Fin Angle Variation Oriented Threshold Voltage Model for a FDSOI FinFET

To support the current level of integration beyond 22 nm, the FinFET architecture is introduced with the expectation of greater levels of device matching. An additional mechanism, arising from charges present at points of disturbance in the silicon lattice in tapering and wavering fins is shown to contribute significantly to transistor mismatch. As the fin is being tapered, quantum mechanical effects come into scene, which contribute to threshold voltage mismatch in the device. This atomic level jogs arise along the taper length of the device can introduce a significant amount of unpassivated charges along the fin. We show that including this mechanism can improve the quantitative understanding of mismatch in FinFETs. For this purpose, an ideal FDSOI FinFET with various fin angles are considered. The existing models are not in agreement with these effects to understand the device better. An analytical model is necessary to relate this mismatch due to differences in threshold voltages with fin angle variation which helps to analyse the influence of the FinFET sidewall inclination angle on the threshold voltage. Threshold voltage and intrinsic trap variations for various fin angles and surface charge densities are measured for analytical study. An optimized threshold voltage equation including the effects of quantum mechanism and channel reduction is developed. The simulations are done through a 3D TCAD simulator Atlas Silvaco and validation of model has done in MATLAB tool.

Transistor mismatch effect on common-mode gain of cross-coupled amplifie

In this paper, the analytical approach of MOS transistor mismatch effect on common-mode gain of cross-coupled amplifier is presented. Transconductance (MOS transistor parameter) mismatch effect on common-mode gain of cross-coupled amplifier was analyzed. This study was started with mathematical derivation for representing the mismatch effect of transconductance between 2 differential pairs of crosscoupled amplifier due to common-mode voltage. The derivation result was simulated based on Monte Carlo simulation with random transconductance mismatch rate from 0.05% until 1%. The common-mode gain increases 36.9 dB and average common-mode gain is -81.1 dB. The transconductance mismatch rate increases followed by increase in common-mode gain. The results can be used by circuit designers to design analog circuits, especially operational amplifier used for biosignals processing to minimize the common-mode gain of their circuits. This research presents aid to circuit designers to improve their circuits performance.

Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion

This brief studies the current mismatch of MOS transistors operating in weak inversion region. Explicit formulas are derived from the drain-current relationship of a long-channel MOS transistor. By referring the drain-current variance to the gate terminal under the small-signal conditions, the dependence of the gate–source voltage on the design parameters and sources of mismatch can be considered. This will help designers to choose the optimum sizes and the efficient $gm/I_{\text {D}}$ ratio for current offset reduction of transistors that their mismatch affects the circuit performance, significantly. In order to confirm the accuracy of the calculated drain-current variance, the hand analysis results are compared with MATLAB simulator outputs. In addition, the input offset of a conventional folded-cascode amplifier is estimated by hand analysis, and the results are compared with SPICE simulator outputs through Monte Carlo analysis.

Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme

An on-chip impedance self calibration methodology for LVSTL (low voltage swing termination logic) for LPDDR4 (low power double data rate) application is proposed. The proposed calibration is to compensate mismatches and variations of the transmitter output drivers due to process and temperature variations. The impedance matching concept uses process sensor and temperature monitoring sensors closely located to DQ pins as a means to detect and compensate the transistor mismatches of the output driver due to process and temperature variations. The proposed circuitry is designed with DRAM bidirectional transceiver and implemented using a 180 nm CMOS technology, and the impedance calibration technique is demonstrated with various external termination resistance of 40/48/60/80/120/240 Ω. In the receiver end, a PMOS input sense amplifier is designed considering the required common mode range for the LVSTL signal interface, and an adaptive gain control scheme is also applied on the receiver design. The process sensor is utilized to adaptively control the gain factor of the receiver. The active area including power-ring of the transmitter is 0.48 mm2 with 0.14 mm2 of the proposed calibration circuit. Since there are 32 transceivers for two channels and the channels share the calibration circuits on the same DRAM die, the area overhead is less than 1.5%. The power consumption of the calibration circuits is 160 μW with 1.8 V power supply at 180 nm CMOS technology node.

(Invited) FDSOI: The Technology Alternative to the Mainstream

At the end of the traditional scaling of CMOS technologies, the industry started to explore paths to push for more performance in chips. This was and has always been driven by the performance-hungry high-end CPU and GPU manufacturers. The main approach was to increase the gate area per chip area by using 3D transistors instead of planar ones, i.e. FinFET. These Fins are very thin, so that in addition to the “double” gate area, the whole conducting channel becomes fully depleted. This reduces the short channel effects dramatically and thus enables a significant shrink of the channel length. However, the manufacturing of FinFET CMOS turned out to be very complex and thus costly. It took the industry more than 10 years to introduce it, first time at the 22nm node in 2011 [1]. Due to this non-planar device architecture, the chip design became much more complex so that only few design houses could afford it. In the last few years, a new trend emerged in semiconductor industries: Connecting everything with everything, also called the Internet of Things (IoT). For this space of applications, computing power does not matter as much as low leakage and/or low dynamic power at low cost. With 22FDX, GLOBALFOUNDRIES offers a technology with less complexity than FinFET, same gate length scaling due to fully-depleted channels, and additional features like back-gate biasing which perfectly suits the IoT market needs [2]. This technology offers nFET (pFET) drive currents of 910µA/µm (856µA/µm) at 0.8V and 100nA/µm leakage. It can be extended down to pA/µm transistor and pA/bitcell leakages for ultra-low leakage applications and below 0.4V Vdd operation for ultra-low dynamic power applications. At the same time, it offers RF/analog characteristics superior to FinFET with fT/fMAX of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively, which serves a huge range of RF and millimeter wave applications. 22FDX also offers a competitive SRAM bitcell with competitive 1.46mV-μm FinFET-like transistor mismatch coefficient (AVt). Extremely low minimum operating voltages (Vmin) are reported for both the high-density (HD) 0.110μm2 and high-current (HC) 0.124μm2 bitcells without any assist, showing 95% limited yield (LY) Vmin values of 0.6V and 0.5V for 64Mb HD and 128Mb HC arrays, respectively [3]. The co-integration of SOI and bulk devices on the same wafer expands the device suite to very efficient diodes, bipolar devices, capacitors, and LDMOS. Main features are FDSOI substrate for nFET, SiGe channel for pFET and dual in-situ doped raised source/drain epitaxy. Despite the utilization of the majority of process steps from the 28nm technologies, a logic/SRAM die scaling of 0.72x/0.83x relative to the 28nm technology node is achieved. All of the above combined enables cost-efficient manufacturing. Back-gate biasing is a unique feature in FDSOI technologies which allows altering the I/V curves of individual devices up to whole blocks of circuitry to boost performance or minimize leakage wherever needed. This feature gives an additional degree of freedom to circuit and chip designers to optimize their products. Some examples will be shown. Furthermore, GLOBALFOUNDRIES is in development of 12FDX, the next FDSOI technology node, which offers further area scaling at enhanced performance and extended features.

A novel low offset low power CMOS dynamic comparator

This paper presents a novel fully dynamic double tail dynamic comparator that exhibits low offset voltage compared to the traditional dynamic comparators. This paper comprises a novel fully differential double tail high performance comparator suitable for low-voltage low-power applications. A fully differential double tail comparator has been intended to meet the necessity of low offset voltage with optimum power with relatively high speed. In this paper expression for the calculation of the offset voltage and delay of the proposed comparator are derived. These expressions corroborate previously stated results with analytical support as well as providing useful insight for the design of dynamic comparator by analyzing the influence of each transistor pair individually. Transistor mismatch analysis is carried out for offset voltage to fully explore the trade-offs in the design of comparator. The results are validated by Monte Carlo simulations and corner analysis. It is shown that in proposed comparator offset voltage is significantly reduced with optimum power. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in 180 nm CMOS technology with ?ý0.9 V supply. The Post-layout simulation results illustrates that a comparator designed with the proposed techniques is 45% faster, and 30% more power efficient and exhibits 91% low offset as compared with conventional comparator, which is the fastest among the conventional comparators.

Study of the operation and SET robustness of a CMOS pulse stretching circuit

This paper analyzes the normal response and the sensitivity to Single Event Transients (SETs) of a CMOS pulse stretching circuit used for the SET pulse width measurement. The pulse stretcher based on two cascaded asymmetrically sized inverters, designed in IHP's 130 and 250nm bulk CMOS technologies, has been studied. Results from SPICE simulations have confirmed that both the normal response (pulse stretching) and the SET robustness (critical charge) of the pulse stretcher are dominantly influenced by the PMOS-to-NMOS sizing ratio. In addition, the operation and SET robustness of the pulse stretcher are influenced by the load, operating temperature, supply voltage variations, process corners and parasitic capacitances of interconnections. The typical process-induced mismatch in transistors' sizes is not a critical issue in this case. It was demonstrated that the multi-stage pulse stretching configuration is more suitable for obtaining wider pulses, but on the other hand is more susceptible to SETs than the single-stage (two-inverter) pulse stretcher. Based on the acquired results, a general approach for the design of a CMOS pulse stretcher, taking into consideration the impact of all analyzed parameters on its normal response and SET robustness, has been proposed.