Quantification of Substrate Current Caused by an Individual Trap at Different Locations and Energies, Prevailing on Si/SiO₂ Interface or Si Substrate of n-MOSFETs

Abstract

Traps on Si/SiO₂ interface or Si substrate are a big source of variability that cause the mismatch of transistors’ performance and leads to failure. To have a comprehensive view of individual traps, causing random fluctuations, variable trap locations are considered on Si/SiO₂ interface and Si substrate. Each trap location is filled with a trap alternatively and simulated via Sentaurus TCAD at five different energy levels (0.35-0.55 eV with a difference of 0.05 eV). The electron charge pumping cycle is recorded to understand each trap