MIS Capacitors Research Articles

Impact of PECVD deposition on dielectric charge and passivation for n-GaN/SiO[formula omitted] interfaces

Controlling properties of GaN/dielectric interfaces is crucial for determining the characteristics of MOS-HEMT devices and their stability. Interface properties are largely affected by the techniques and specific conditions of dielectric deposition. In this work, a Taguchi design of experiment was applied to study the effect of plasma parameters during deposition of SiOx by PECVD for passivation of n-GaN. SiOx/GaN MIS capacitors were fabricated and characterized by capacitance measurement at a high probing frequency of 1 MHz. The interface states density, hysteresis and flatband voltage were analyzed and modeled in relation with the flow of SiH4, plasma power, chamber pressure and temperature. Excellent fits could be obtained on a single model including linear terms for all studied parameters and quadratic terms for the flow of SiH4 and temperature. We show that it is possible to obtain some control of the flatband voltage while maintaining a good interface quality. Positive flatband voltages are potentially of interest to enable normally-off operation for MOS-HEMTs and this could be obtained mainly by using a high SiH4/N2O ratio. To the contrary, negative flatband voltage values often ensure the most stable operation of MOS-HEMTs and this was achieved with a low SiH4/N2O and high plasma power. MIS capacitors with near-zero flatband voltage were also obtained with low SiH4/N2O ratio and low plasma power. Hysteresis and interface states density in relation with deposition plasma conditions are also analyzed in order to offer the best trade-offs depending on the end applications of MOS-GaN devices. By demonstrating the great impact of plasma conditions during dielectric deposition on electronic properties of MIS devices, we show that the process of gate insulation can be optimized to simultaneously control the density of defects and fixed charge at the interface.

Development and Characterization of an Advanced Voltage-Controllable Capacitor Based on AlInGaN/GaN-Si (111) Epitaxy

The AlInGaN/GaN heterojunction epitaxy material with high cutoff frequency and saturated power density has become a very popular candidate for millimeter wave applications in next-generation mobile communication. In this study, an advanced voltage-controllable capacitor based on the AlInGaN/GaN-Si (111) epitaxy was proposed by employing a bi-directional series MIS capacitor structure. The capacitor was fabricated by using a pad area of 40 μm × 40 μm, with a 1 μm distance between the positive and negative electrodes. The test results show that the capacitance is turned on with a saturation capacitance density and a maximum leakage current density of 0.30 fF/μm2 of 0.37 pA/μm2, respectively, for the control voltage from −6.5 V to 6 V. In particular, in the proposed design method, the saturation capacitance required for the practical application can be obtained by simply adjusting the capacitance area. The capacitor showcases characteristics of rapid turn-on and turn-off responses coupled with low loss, underscoring its promising prospects for deployment in RF switching applications.

Improved electrical performance for SiO2/β-Ga2O3 (001) MIS capacitor by post-deposition annealing

In this study, we have fabricated a high-performance SiO2/β-Ga2O3 (001) MIS capacitor and investigated the effect of low-temperature post-deposition annealing (PDA) on its electrical properties. The SiO2/β-Ga2O3 (001) MIS capacitor exhibits improved gate leakage current and breakdown electrical field after the PDA treatment. The high-frequency capacitance-voltage hysteresis curves reveal that the fixed charge density, as well as the fast and deep near-interfacial trapped charge densities, decreases with the PDA process. We achieved an interfacial trapped charge density as low as 1.6 × 1011 cm−2 eV−1 at an energy of 0.6 eV below the conduction band of β-Ga2O3 (001) through 400 °C annealing.

Investigation of atomic layer deposition methods of Al2O3 on n-GaN

In this work, three atomic layer deposition (ALD) approaches are used to deposit an Al2O3 gate insulator on n-GaN for application in vertical GaN power switches: thermal ALD (ThALD), plasma-enhanced ALD (PEALD), and their stacked combination. The latter is a novel method to yield the most ideal insulating layer. Also, the influence of an in situ NH3 or H2 plasma pre-treatment is studied. Planar MIS capacitors are used to investigate the electrical properties and robustness of the gate insulators. In vacuo x-ray photoelectron spectroscopy (XPS) is used to study the changes in chemical composition after every surface treatment. XPS shows that all plasma pre-treatments efficiently remove all carbon contamination from the surface, but only NH3 plasma is observed to additionally remove the native oxide from the n-GaN surface. The water precursor step in the ThALD process does not completely remove the CH3 ligands of the trimethylaluminum precursor step, which might electrically be associated with a reduced forward bias robustness. The O2 plasma step in the PEALD process is associated with the removal of carbon and a tremendous increase of the O content in the GaN surface region. Electrically, this strongly correlates to an enhanced forward bias robustness and an increased forward bias hysteresis, respectively. The ThALD/PEALD stack method mitigates the shortcomings of both ALD processes while maintaining its advantages. Electrical measurements indicate that the stack method alongside NH3 plasma pretreatment provides the best characteristics in terms of hysteresis, threshold voltage, forward bias robustness, and interface trap density of states.

Carrier conduction mechanisms in MIS capacitors with ultra-thin Al2O3 at cryogenic temperatures

In this work, a study comprising the electrical characterization and analysis of the electrical response of metal–insulator–semiconductor Al/Al2O3/Si capacitors in a temperature range from ambient temperature down to 3.6 K is presented. An ultra-thin 6 nm Al2O3 film, deposited by atomic layer deposition, was used as an insulating layer. Current–voltage and electrical stress measurements were performed on the capacitors in the specified temperature range, and the experimental data obtained were analyzed using current transport equations to model the conduction mechanisms that allow charge transport through the Al2O3. Energetic parameters associated with trap levels within the Al2O3 bandgap corresponding to the Poole–Frenkel emission and trap-assisted tunneling mechanisms were obtained, and their temperature dependances were studied and associated with the presence of physical material defects. The analysis of the modeling results points to trap-assisted tunneling as the dominant mechanism at low temperatures for intermediate electric field values. Additional phenomena that limit charge transport were also observed, such as charge trapping in the bulk of the Al2O3 upon the application of electrical stress at ambient temperature and silicon freeze out at cryogenic temperatures. Our findings constitute an effort at understanding the physical phenomena that govern the electrical behavior of thin-film Al2O3-based capacitors, especially at cryogenic temperatures, given that these materials and devices are of considerable importance for applications in CMOS-based cryoelectronics and quantum technologies, among others.

Photodetectors based on chemical vapor deposition or liquid processed multi-wall carbon nanotubes

Carbon nanotubes (CNTs) have attracted great interest for applications due to their unique mechanical, electronic and optoelectronic properties. The advantages of the multiple wall carbon nanotubes for optoelectronic devices like photodetectors and photodiodes are the large effective photo-collector surface as well as the possibility to tune the band gap and absorbance by controlling the growth parameters. In this work, we demonstrate two types of hybrid Multi-Wall CNTs/Si3N4/n-Si photodetectors based on ordered (produced with Chemical Vapor Deposition – CVD) and solution processed MWCNTs and evaluate their performance in UV and visual spectrum (275 nm, 655 nm). Device parameters were obtained by comparison of I–V characteristics to Schottky barrier models and C–V characteristics to standard MIS capacitor models. The role of silicon nitride layer was also examined by comparing devices with different nitride layer thickness. Focusing on the UV part of the spectrum, the solution processed device was photosensitive in the voltage range 3V–6V giving its best performance (External Quantum Efficiency - E.Q.E. 85%@275 nm) at 5V and illumination of 5 μW. The CVD processed device showed lower EQE for the same bias voltage range. Both devices showed a low performance in optical part of the spectrum compared to the corresponding one in the UV part of the spectrum. The mean optical responsivity values obtained at the UV part of the spectrum in both cases indicate that the Visible light blind MWCNT/Si3N4/n-Si system have a potential use in UV photodetector applications. In particular, solution processed devices may pave the way for cheap production of UV sensor systems.

Nonthermal Equilibrium Process of Charge Carrier Extraction in Metal/Insulator/Organic Semiconductor/Metal (MIOM) Junction

This paper presents the concept and experimental evidence for the nonthermal equilibrium (NTE) process of charge carrier extraction in metal/insulator/organic semiconductor/metal (MIOM) capacitors. These capacitors are structurally similar to metal/insulator/semiconductor/(metal) (MIS) capacitors found in standard semiconductor textbooks. The difference between the two capacitors is that the (organic) semiconductor/metal contacts in the MIOM capacitors are of the Schottky type, whereas the contacts in the MIS capacitors are of the ohmic type. Moreover, the mobilities of most organic semiconductors are significantly lower than those of inorganic semiconductors. As the MIOM structure is identical to the electrode portion of an organic field-effect transistor (OFET) with top-contact and bottom-gate electrodes, the hysteretic behavior of the OFET transfer characteristics can be deduced from the NTE phenomenon observed in MIOM capacitors.

Comparison of CoW/SiO2 and CoB/SiO2 Interconnects from the Perspective of Electrical and Reliability Characteristics

As the feature size of integrated circuits has been scaled down to 10 nm, the rapid increase in the electrical resistance of copper (Cu) metallization has become a critical issue. To alleviate the resistance increases of Cu lines, co-sputtered CoW and CoB alloying metals were investigated as conductors and barriers in this study. Annealing CoM (M = W or B)/SiO2/p-Si structures reduced the resistivity of CoM alloys, removed sputtering-deposition-induced damage, and promoted adhesion. Additionally, both annealed CoW/SiO2 or CoB/SiO2 structures displayed a negligible Vfb shift from capacitance-voltage measurements under electrical stress, revealing an effective barrier capacity, which is attributed to the formation of MOx layers at the CoM/SiO2 interface. Based on the thermodynamics, the B2O3 layer tends to form more easily than the WOx layer. Hence, the annealed CoB/SiO2/p-Si MIS capacitor had a higher capacitance and a larger breakdown strength did than the annealed CoW/SiO2/p-Si MIS capacitor.

Comparison of on-chip MIS capacitors based on stacked HfO2/Al2O3 nanolaminates

High- κ dielectric materials are commonly used in microelectronic components due to the technological necessity of increasing the capacitance density of dielectric layers. The thickness of the layer is a crucial parameter of this technology because it has a significant influence on dielectric properties, capacitance density, leakage current density–voltage ( J–V ), breakdown voltage, and capacitance density–voltage ( C–V ). Among metal oxide compounds, HfO 2 and Al 2 O 3 have been widely studied due to their good thermodynamic stability in contact with silicon. Thus, in this study, devices are fabricated by atomic layer deposition (ALD) processes on Si wafer. Properties of HfO 2 /Al 2 O 3 -based stack dielectric as on-chip MIS capacitors are investigated. The capacitance density, C–V , J–V , impedance characteristics, equivalent dielectric constant, breakdown voltage, and leakage current are studied on stacks (HfO 2 /Al 2 O 3 ) with a thickness ratio of 1:1. The experimental results indicate very good leakage current and good breakdown voltage. Oxygen vacancies play a significant role in increasing the conductance and contrarily decreasing the equivalent dielectric constant of the stack.

Development of all-solution processed CdSe thin film phototransistors with hybrid TiSiOx-PVP dielectric gate

We report a simple solution process to obtain hybrid TiSiOx-PVP dielectric films, at different molar concentrations, for dielectric gate applications in CdSe-based photo TFT. A set of hybrid films was deposited by spinning the precursor solutions with 1:1:1, 1:2:1, and 1:2:2 molar concentrations of PVP:SiO2:TiO2, respectively. These samples were analyzed by several experimental techniques. MIM and MIS capacitors were assembled to determine the hybrid films dielectric properties. The leakage current density was in the range of 10−8-10−5 A/cm2 at an electric field from 0 to 0.2 MV/cm, with a dielectric constant in the range from 4 to 8 at 1 MHz, depending on the composition. The hybrid layers were applied to the fabrication of solution-processed CdSe TFT on ITO-coated glass substrates. The all-solution processed TFT showed the capability for photodetection in a wide light wavelength range, operating at low voltage with very low hysteresis, mobility of 0.17 cm2/Vs, low threshold voltage of 1 V, low subthreshold swing of 0.17 V/dec, and on/off current ratio of 105.

Channel characteristics of ferroelectric organic High-K dielectric asymmetric metal insulator semiconductor capacitor

In the present work, it is demonstrated that an asymmetric organic MIS (AMIS) capacitor utilizing sandwiched ferroelectric material between high k-dielectric as an insulator and pentacene as an active semiconductor can be used for a wide range of sensing applications. The capacitive test structure is simpler in fabrication and characterization and is less sensitive to defect states since it utilizes a strong accumulation region. The polarization behavior of the ferroelectric materials enables higher charge density in the channel thereby reducing channel resistance and thus increasing the channel capacitance. This property of the Ferro-based AMIS structure enables the extraction of OTFT parameters and also serves as a platform for sensing applications. The use of high-k dielectric material both as an insulator and buffer layer makes the technique more robust against lattice mismatch and high-power dissipation. The channel characteristics are free from the contact resistance effect due to the large characteristics channel length at a smaller frequency that makes the technique unique. 2-D numerical simulation with Pentacene/Ferro geometry and gold/ITO as top/bottom contact configuration has been simulated to demonstrate the concept and the model. (a) C-V without high k dielectric and without ferro, (b) C-V only with high k dielectric and (c) C-V with high k dielectric and with ferro material. • The channel capacitance of the conventional AMIS structure can be increased significantly by employing a ferroelectric material. • This property can be suitably used for extracting accurate TFT channel properties and also for sensing applications.

Influence of substrate biasing on structural, chemical and electrical properties of Al2O3 thin films deposited by PEALD

High-k materials are needed to minimise the gate leakage current in high-speed and high-power switching applications. In this regard, aluminium oxide (Al2O3) deposited by plasma enhanced atomic layer deposition (PEALD) is gaining extensive attention to be used as high-k material in microelectronics. In this work, we studied the effect of substrate biasing during the oxidizing plasma step on physical, chemical and electrical properties of Al2O3 thin films grown by PEALD on silicon substrate. We show that the structural and electrical properties such as the flat band voltage, and chemical composition can be tuned with the applied substrate bias. Indeed, we highlight that the dielectric constant of the MIS capacitor decreases from 8.5 to 6.5 and the charge polarity of the film is modulated from negative to positive when the applied substrate bias is increased. Using morphological and structural characterisations, we show that the substrate bias significantly affects the chemical composition of Al2O3 thin film layer. Moreover, we highlight by cross-sectional transmission electron the presence of an interfacial layer between Si and Al2O3 which could significantly influence the electrical properties of the deposited thin film. The chemical composition of this interfacial layer can be controlled by the applied substrate bias. Using a series of energy dispersive x-ray experiments, we further confirm the formation of aluminosilicate under low substrate bias condition while silicon oxide is formed under high bias. These findings show that the substrate biasing plays a critical role in defining physical, chemical as well as electrical properties of the PEALD Al2O3 thin films.

Comparison of On-Chip Mis Capacitors Based on Stacked Hfo2/Al2o3 Nanolaminates

Comparison of On-Chip Mis Capacitors Based on Stacked Hfo2/Al2o3 Nanolaminates

Transparent MIS capacitors on plastic substrates fabricated by high-frequency ultrasonic spray pyrolysis

Transparent MIS capacitors on plastic substrates fabricated by high-frequency ultrasonic spray pyrolysis

Effect of blocking and tunnel oxide layers on the charge trapping properties of MIS capacitors with ALD HfO2/Al2O3 nanolaminated films

Electrical and charge trapping properties of HfO2/Al2O3 nanolaminated stacks incorporated in three types of metal-insulator-silicon capacitor structures (without blocking and tunnel oxide layers; with 20 nm Al2O3 as blocking oxide and ∼3 nm Al2O3 or thermal SiO2 as tunnel layer) were investigated. HfO2/Al2O3 stacks exhibit a positive initial oxide charge, and adding of the 3 nm Al2O3 tunnel layer to the capacitor doubles the amount of the positive charge and the density. Using SiO2 as a tunnel layer resulted in a negative initial oxide charge which is interpreted by the effect of dipole formation at the Al2O3/SiO2 interface. Tunnel SiO2 provides lowest density of the interface states at silicon and leakage currents. The insertion of blocking and tunnel oxide layers to the capacitors significantly widens the memory windows; capacitors with a SiO2 tunnel oxide demonstrate largest memory windows.

Impact of oxide gate electrode for ferroelectric field-effect transistors with metal-ferroelectric-metal-insulator-semiconductor gate stack using undoped HfO2 thin films prepared by atomic layer deposition

Ferroelectric field-effect transistors (FETs) with a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) gate stack were fabricated and characterized to elucidate the key process parameters and to optimize the process conditions for guaranteeing nonvolatile memory operations of the device when the undoped HfO2 was employed as ferroelectric gate insulator. The impacts of top gate (TG) for the MFM part on the memory operations of the MFMIS-FETs were intensively investigated when the TG was chosen as metal Pt or oxide ITO electrode. The ferroelectric memory window of the MFMIS-FETs with ITO/HfO2/TiN/SiO2/Si gate stack increased to 3.8 V by properly modulating the areal ratio between two MFM and MIS capacitors. The memory margin as high as 104 was obtained during on- and off-program operations with a program pulse duration as short as 1 μs. There was not any marked degradation in the obtained memory margin even after a lapse of retention time of 104 s at 85 °C and repeated program cycles of 10,000. These obtained improvements in memory operations resulted from the fact that the choice of ITO TG could provide effective capping effects and passivate the interfaces.

Reliable and precise determination of interface states in metal–insulator–polymeric semiconductors devices

The major objective of this manuscript is to develop an integrable capacitance-voltage (C-V) model for the extraction of the interfacial states at p-type polymeric semiconductor-insulator-metal (MIPS) capacitors. A polymeric P3HT (3-hexylthiophene) semiconductor-insulator-metal device was fabricated, firstly. Then, an integrable C-V model was developed. The model was based on Fermi-Dirac distribution for holes and experimental C-V of the p-type polymeric MIS. By the least square nonlinear curve fitting, good matches are presented between theoretical and experimental C-V plots for our p-type P3HT MIS capacitor. With nonlinear regression technique, the capacitance of polymeric MIS not only can be explained via voltage, but also can be predicted by frequency. Hence, the static C-V of polymeric MIS was successfully extracted and therefore the surface state density of polymeric MIS was evaluated via quasi-static technique. Because the suggested model is integrable, surface potential and the interfacial state density can be obtained with reliable, precise and simple method and over whole range of the energy gap on polymeric MIS in explicit functional form for the first time. The linear and non-linear electric potential were determined by applying integral of C-V model over whole voltage. The amount of the charge in channel region was determined by integrating model of C-V over all surface potential. This C-V model has been used to detect the charge on per unit area in channel too. Evidence is presented suggesting that more electrical information of polymeric MIS can be obtained via analysis on C-V characteristics using the suggested model.

Nonlinear Impedance Spectroscopy of Organic MIS Capacitors and Planar Heterojunction Diodes

We present a nonlinear impedance spectroscopy technique and demonstrate its ability to directly measure nonlinear processes including electron-hole recombination and space charge effects in organic-semiconductor-based diodes and MIS capacitors. The method is based on Fourier analysis of the measured higher harmonic current response to an AC voltage signal. Characterization of the higher harmonic response allows nonlinear impedance spectroscopy to measure material and device properties over a wide range of frequencies, which would otherwise be impossible using conventional impedance spectroscopy. As the higher harmonic signals are purely a product of nonlinear processes, they are independent of the linear device capacitance and resistance. This allows space charge and recombination effects to be investigated at several orders of magnitude higher frequency without fitting to an equivalent circuit model.

Admittance characterization of pentacene metal-insulator-semiconductor capacitors with SiO2 and SiO2/Ga2O3 insulators in temperature range of 9–300 K

Pentacene-based metal-insulator-semiconductor capacitors with SiO2 and SiO2/Ga2O3 insulators were investigated in the temperature range of 9–300 K. The capacitance-voltage curves of the fabricated capacitors had virtually no hysteresis when using SiO2 as an insulator. The hole concentration values, determined using the Mott–Schottky analysis, were in the range of (1.0–1.3) × 1018 cm–3, depending on the substrate used. It is shown that the hole concentration remains constant over a wide range of frequencies and temperatures. It is shown that the type of the substrate (SiO2 and SiO2/Ga2O3) significantly affects the electrical characteristics of pentacene MIS capacitors. A pentacene film grown on SiO2 substrate was found to have a shallow level with activation energy of about 3 meV. For the case of using SiO2/Ga2O3 substrate, trap levels with activation energies of (5.5–6.0) and (480–570) meV were revealed.

Fabrication and Characterization of amorphous Lanthanum Zirconate Gate Capacitors

A novel high-k gate dielectric material, i.e., Lanthanum-doped Zirconium oxide (La-doped ZrO2), has been thoroughly studied for applications in future metal oxide semiconductor field-effect transistor (MOSFET). The film's structural, chemical and electrical properties are investigated experimentally. The incorporation of La into ZrO2 impacted the electrical properties in terms of leakage current while not sacrificing its dielectric constant. The dielectric constant of 25 is achieved which is calculated from the C-V analysis taken from Agilent 1500A Semiconductor Device Analyzer. XRD, FTIR, EDX analysis were conducted to confirm the stoichiometry and bond formation of La2Zr2O7. The sol-gel spin coating method is adopted to form a uniform thin film over p-Silicon substrate and Aluminium is evaporated in the eBeam technique as gate electrode to form an MIS capacitor. The La-doped ZrO2 film is hence a potential high-k gate dielectric for future application in MIS thin film transistors.