Mirror Circuit Research Articles

Implantable Devices with Reconfigurable Biosensing Analog Front End

This paper, have a tendency to develop a reconfigurable analog front end for wireless body sensing element nodes and implantable devices with reduced size. By converting voltage in to current the effort to achieve the area efficiency is taken. Because these are bio implantable chips if the numbers of transistors are reduced it will reduce lots of power and area, the circuit operation is also quick. In the proposed system, narrow swing current mirror circuit is used in the low pass filter region. By using the current mirror the same input current can be obtained at the output. At the same time the area of the chip used in the devices gets reduced. The active space of the chip is 157µm2.

Performance Assessment of New Dual-Pocket Vertical Heterostructure Tunnel FET-Based Biosensor Considering Steric Hindrance Issue

In this paper, a new dual-pocket (DP), dielectric modulated (DM) heterostructured tunnel field-effect transistor (DM-HTFET)-based biosensor has been reported. First, the efficacy of the DP-hetero-TFET (HTFET) has been analyzed by comparing it with other existing TFET structures. Next, a comprehensive assessment of sensitivity between single-pocket (SP) and DP-DM-HTFET biosensors for pocket thickness ( ${T}_{\text {pocket}}$ ), pocket length ( ${L}_{\text {pocket}}$ ), pocket doping ( ${N}_{\text {pocket}}$ ), work function of the gate metal, molar fraction of Ge, gate oxide layer, and gate oxide layer thickness ( ${T}_{\text {ox}}$ ) was done. Hence, a nonuniform arrangement of biomolecules inside the cavity simulation has been done using ATLAS device simulation software to validate the working ability of the proposed sensor. Significant improvement in the sensitivity due to threshold voltage (ON-current) i.e., 26.78% (78.5%), 60.8% (40.4%), 56% ( ${2.2} \times {10}^{{2}}$ %), and 40.6% (80.68%) has been observed for the DP-DM-HTFET over SP with the variation of ${T}_{\text {pocket}}$ , ${L}_{\text {pocket}}$ , ${N}_{\text {pocket}}$ , and ${T}_{\text {ox}}$ , respectively. DP-DM-HTFET-based current mirror circuit has also been demonstrated at the end. Sensitivity evaluation discloses that the DP-DM-HTFET can be a promising candidate for CMOS-based label-free biosensing applications.

BIOSENSOR SYSTEM DESIGN FOR DISSOLVED OXYGEN MEASUREMENT USING CURRENT MIRROR CIRCUIT

It has been designed a biosensor system using the current mirror circuit. Biosensor system usually implements an amperometric circuit such as a trans-impedance to measure the current value that flows in the solution due to the dissolved oxygen in it. The trans-impedance circuit causing rather high noise, besides that the power supply used must be bipolar; otherwise the measurement range would be narrower. In this paper, a current mirror circuit is used to convert the flowing current in the solution. The current mirror circuit has a lower noise level, besides the power supply needed is just unipolar, and the measurement range much wider. By utilizing this circuit, the biosensor measurement system can be optimized with its achieved advantages

Design of Differential LNA and Double Balanced Mixer using 180 nm CMOS Technology

The RFICs plays an important role in wireless communication systems due to their effective operation in the 2.4 GHz frequency, popularly known as ISM (Industrial, Scientific and Medical) band. LNA and Mixers are the major components used in transceivers for the purpose of amplification and frequency translation. Such LNAs and mixers are of different kinds and various techniques are used for their optimization. The paper describes the design of a differential LNA with two single stranded source degenerate LNAs with greater increase in gain. differential LNA is combined with Double balanced mixer with a current mirror circuit and BALUN with the bias controlling MOSFETs are used to show the better performance at 2.4 GHz frequency range. CMOS has become a viable technology for the design of high-performance receivers in the Radio Frequency (RF) regime. The conversion gain of 22.28 dB and IF of 595 MHz of Differential LNA with Double Balanced mixer are higher than the cross comparison results of the other methods at 180 nm technology. CMOS implementation of the design is done using the Cadence Virtuoso tool of 180 nm technology at 2.4 GHz frequency and 1.8 V of supply voltage.

A low-voltage gain boosting-based current mirror with high input/output dynamic range

This paper presents a bulk-driven current mirror circuit based on the gain-boosting technique to achieve high input/output dynamic range and high output resistance. The bulk-driven based diode-connected transistor at the input removes the threshold voltage limitation to provide low headroom voltage on the basic transistors. In addition, the auxiliary circuit used in the first gain-boosting structure is a current mode amplifier that is driven by draining current from the main circuit to remove threshold voltage limitation on the input/output swing. In order to achieve higher output resistance, the second gain-boosting structure includes a voltage mode amplifier without creating any limitation on the output swing. Simulation results in a 0.18 ​μm CMOS technology show a maximum output voltage swing of 0.9 ​V under a 1 ​V supply, while the input and output resistances are 68.3 ​Ω and 10.5 ​GΩ, respectively. The current transfer error also changes between −0.085% and +0.075% for an input current range of 1000 ​μA.

Novel wide dynamic range current mirror

A novel cascode current mirror for low-voltage application with larger input dynamic range is presented. The proposed mirror circuit combines the advantages of wide input swing, wide output swing and large output resistance capability. It is suitable for low-voltage and low-power application. Simulation results show that the circuit work properly for the input current ranges of 10 [Formula: see text]A to 1 mA and bandwidth is 5.02 GHz for 1 mA DC component.

Biosensor signal improvement using current mirror topology for dissolved oxygen measurement

A biosensor system for dissolved oxygen level detection based on a current mirror method has been designed and characterized. Most biosensor systems implement a transimpedance circuit to convert the flowing current on the sensor to an output voltage signal. These systems are voracious and susceptible to instability and noise due to the configuration of the circuit used. The power supply is also impractical due to the bipolar polarity needed, and the systems consume more power since they use more active devices in the op-amp. These disadvantages need to be overcome when special requirements are needed such as low-noise measurement in dissolved oxygen level detection, and for battery-powered and low-power devices for in situ and remote area measurement. Differing from transimpedance, current mirror circuits convert the flowing current to the output voltage by copying the current with a ground-referenced input and output, and use fewer active devices. The proposed current mirror circuit aims to diminish the noise of the output and minimize the power consumption through reducing the active devices used. The results show some significant signal quality improvements when using the current mirror circuit, where the noise response of the current mirror circuit is ten times lower than the transimpedance circuit.

Low-cost multi electrode resistivity meter based on microcontroller for electric resistivity tomography purpose

This study was conducted to make Multi Electrode Resistivity Meter with simple and low-cost circuit design. The instrument that has been made use switching mode boost converter for increasing the voltage with Arduino Nano as a source of PWM signal connected to the boost converter circuit, and cascode current mirror circuit is used for constant current source. The sensor on this resistivity meter using the voltage divider circuit for voltage sensor, and non-inverting OPAMP circuit for current sensor. Multi electrode circuit using relay module connected with IC74HC595 and controlled by Arduino MEGA 2560. This instrument is integrated with GUI that serves as controller and data display. There are several measurements for this instrument that is maximum resistance on each constant current generated from the circuit, repeatability and reproducibility measurement, sensor calibration measurement, and ERT measurement with three configuration i.e wenner configuration, wenner-schlumberger configuration, and dipole-dipole configuration on soil samples.

Self-Sensing Vibration Suppression of Piezoelectric Cantilever Beam Based on Improved Mirror Circuit

The self-sensing technique allows a single piece of piezoelectric element to function simultaneously as an actuator and a sensor in a closed-loop system. This study proposes an improved vibration suppression system using the piezoelectric self-sensing technique whose usefulness is experimentally verified in a cantilever beam. A single piezoelectric element is bonded to the root of the beam and functions as an actuator and a sensor simultaneously. A mirror circuit constructed with two charge driver circuits is used to pick up the sensing signal from the driving voltage signal. Then, a closed-loop control strategy based on the proportion integration differentiation (PID) algorithm can adjust the sensing signal precisely to suppress the vibration of the cantilever beam quickly. The first mode of vibration is suppressed, and the amplitude of the vibration is actively dampened by a factor exceeding 96.4%. Moreover, the frequency sweep experiments demonstrate that with the PID feedback control circuit connected to the piezoelectric cantilever beam, the Q value of the system is greatly reduced, and the loss factor is increased from 0.053 to 0.288. The improved mirror circuit with PID control has a good suppression effect in the frequency range near the first order mode of the cantilever beam.

Development of a current mirror-integrated pressure sensor using CMOS-MEMS cofabrication techniques

PurposeThis paper aims to describe the fabrication and characterization of current mirror-integrated microelectromechanical systems (MEMS)-based pressure sensor.Design/methodology/approachThe integrated pressure-sensing structure consists of three identical 100-µm long and 500-µm wide n-channel MOSFETs connected in a resistive loaded current mirror configuration. The input transistor of the mirror acts as a constant current source MOSFET and the output transistors are the stress sensing MOSFETs embedded near the fixed edge and at the center of a square silicon diaphragm to sense tensile and compressive stresses, respectively, developed under applied pressure. The current mirror circuit was fabricated using standard polysilicon gate complementary metal oxide semiconductor (CMOS) technology on the front side of the silicon wafer and the flexible pressure sensing square silicon diaphragm, with a length of 1,050 µm and width of 88 µm, was formed by bulk micromachining process using tetramethylammonium hydroxide solution on the backside of the wafer. The pressure is monitored by the acquisition of drain voltages of the pressure sensing MOSFETs placed near the fixed edge and at the center of the diaphragm.FindingsThe current mirror-integrated pressure sensor was successfully fabricated and tested using in-house developed pressure measurement system. The pressure sensitivity of the tested sensor was found to be approximately 0.3 mV/psi (or 44.6 mV/MPa) for pressure range of 0 to 100 psi. In addition, the pressure sensor was also simulated using Intellisuite MEMS Software and simulated pressure sensitivity of the sensor was found to be approximately 53.6 mV/MPa. The simulated and measured pressure sensitivities of the pressure sensor are in close agreement.Originality/valueThe work reported in this paper validates the use of MOSFETs connected in current mirror configuration for the measurement of tensile and compressive stresses developed in a silicon diaphragm under applied pressure. This current mirror readout circuitry integrated with MEMS pressure-sensing structure is new and fully compatible to standard CMOS processes and has a promising application in the development CMOS-MEMS-integrated smart sensors.

A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits

A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits

Formation of Field Reversed Configuration (FRC) on the Yingguang-I device

As a hybrid approach to realizing fusion energy, Magnetized Target Fusion (MTF) based on the Field Reversed Configuration (FRC), which has the plasma density and confinement time in the range between magnetic and inertial confinement fusion, has been recently widely pursued around the world. To investigate the formation and confinement of the FRC plasma injector for MTF, the Yingguang-I, which is an FRC test device and contains a multi-bank program-discharged pulsed power sub-system, was constructed at the Institute of Fluid Physics (IFP), China. This paper presents the pulsed power components and their parameters of the device in detail, then gives a brief description of progress in experiments of FRC formation. Experimental results of the pulsed power sub-system show that the peak current/magnetic field of 110 kA/0.3 T, 10 kA/1.2 T and 1.7 MA/3.4 T were achieved in the bias, mirror and θ-pinch circuits with quarter cycle of 80 μs, 700 μs and 3.8 μs respectively. The induced electric field in the neutral gas was greater than 0.25 kV/cm when the ionization bank was charged to 70 kV. With H2 gas of 8 Pa, the plasma target of density 1016 cm−3, separatrix radius 4 cm, half-length 17 cm, equilibrium temperature 200 eV and lifetime 3 μs (approximately the half pulse width of the reversed field) have been obtained through the θ-pinch method when the bias, mirror, ionization and θ-pinch banks were charged to 5 kV, 5 kV, 55 kV and ±45 kV respectively. The images from the high-speed end-on framing camera demonstrate the formation processes of FRC and some features agree well with the results with the two-dimension magneto hydrodynamics code (2D-MHD).

Hexapod Type MEMS Microrobot Equipped with an Artificial Neural Networks IC

This paper proposes a hexapod type microrobot controlled by an artificial neural networks IC. The structural component of the microrobot is produced by micro electro mechanical systems (MEMS) process. The rotary actuator inside the robot is composed of the artificial muscle wire of shape memory alloy (SMA) material. The artificial neural networks IC includes cell body models, inhibitory synaptic models and current mirror circuits. By reducing the heat capacity of the actuator and the length of electrical wire to the actuator, the walking speed achieved 12 mm/min.

Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures

The goal of this work is to study the performance of current mirror circuits designed with line tunnel field effect transistor (TFET) devices and compare the suitability of this technology with alternatives such as point TFETs and FinFETs. Experimental results have been obtained at room and high temperatures and the analyses focused on parameters such as the magnitude of the on-state current and the sensitivity of the current transfer ratio to channel dimensions mismatch and to the temperature. Line TFETs exhibited higher on-state current than point TFETs, in spite of a higher susceptibility to the channel length. When band-to-band tunneling prevails for both input and output transistors, the current transfer ratio with line TFETs presented a nearly linear dependence on the temperature due to bandgap narrowing. This way, a general equation of the current transfer ratio for circuits designed with the three highlighted technologies is proposed. Globally, it was observed that, unless a very low sensitivity to channel length mismatch is required, line TFET devices are a very suitable alternative for current mirror circuits, since this technology provides much higher on-state currents than point TFETs, and at the same time it is much less sensitive to temperature variations than FinFET transistors.

Cognitive Control Structures in the Imitation Learning of Spatial Sequences and Rhythms-An fMRI Study.

Imitation learning involves the acquisition of novel motor patterns based on action observation (AO). We used event-related functional magnetic resonance imaging to study the imitation learning of spatial sequences and rhythms during AO, motor imagery (MI), and imitative execution in nonmusicians and musicians. While both tasks engaged the fronto-parietal mirror circuit, the spatial sequence task recruited posterior parietal and dorsal premotor regions more strongly. The rhythm task involved an additional network for auditory working memory. This partial dissociation supports the concept of task-specific mirror mechanisms. Two regions of cognitive control were identified: 1) dorsolateral prefrontal cortex (DLPFC) was found to be more strongly activated during MI of novel spatial sequences, which allowed us to extend the 2-level model of imitation learning by Buccino et al. (2004) to spatial sequences. 2) During imitative execution of both tasks, the posterior medial frontal cortex was robustly activated, along with the DLPFC, which suggests that both regions are involved in the cognitive control of imitation learning. The musicians' selective behavioral advantage for rhythm imitation was reflected cortically in enhanced sensory-motor processing during AO and by the absence of practice-related activation differences in DLPFC during rhythm execution.

Robust fuzzy SRAM for accurate and ultra‐low‐power MVL and fuzzy logic applications

A fuzzy static RAM (SRAM) is proposed, which is applicable in fuzzy logic and many multiple-valued logic (MVL) applications. The new structure is basically an extension to the binary SRAM cell. Two cross-coupled voltage mirror circuits are used to be able to hold an arbitrary voltage value. The proposed design forms a robust and reliable structure, which is capable of operating with more than 95% accuracy in spite of imperfect fabrication of carbon nanotube FETs. Another exceptional advantage is its ultra-low-power consumption in MVL environments. It consumes 38.7 and 99% less static power compared with the SRAMs with regular ternary and quaternary components, respectively.

Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology

Smart Power integrated circuits receive an increasing attraction recently, especially in automotive industry. Substrate noise coupling is one of the major causes of failure in this kind of integrated circuits that requires circuit redesign and increases the overall cost. An exhaustive failure analysis is needed to identify failures due to substrate coupling. In this paper, we present a post-layout extraction and simulation methodology for substrate parasitic modeling. Based on this methodology, we have developed a dedicated computer-aided-design tool that is used for substrate extraction from layout patterns. The extraction employs a meshing algorithm for substrate parasitic generation. To validate the substrate model, the process of benchmarking uses industrial design structures in $0.35\mu m$ high-voltage-CMOS technology. Two test cases in transient simulation are considered in this work. The first one is a common used current mirror circuit. Our tool predicts the interference of substrate currents to this basic circuit. The second test case is an industrial design test-chip where parasitic coupling is investigated in a standard automotive test. Eventually, by using the proposed CAD tool, it becomes possible to simulate the behaviors of substrate noise at early phase before fabrication.

Design of current mirror integration ROIC for snapshot mode operation

Current mirror integration (CMI) read out integrated circuit (ROIC) topology provides a low input impedance to photo-detectors and provides large injection efficiency, large charge handling capacity and snapshot mode operation without in-pixel opamps. The ROIC described in this paper has been implemented with a modified current mirror circuit, with matched PMOS pairs for detector input stage and its biasing. The readout circuit has been designed for 30 × 30 μm2 pixel size, 4 × 4 array size, variable frame rate, 5 Mega pixel per second (Mpps). Experimental performance of the test chip has achieved 15 Me charge handling capacity, a high dynamic range of 83 dB, 99.8% linearity and 99.96% injection efficiency. The ROIC design has been fabricated in 3.3 V 1P6M UMC 180 nm CMOS process and tested up to 5 MHz pixel rate at room and at cryogenic temperature.

Output impedance improvement of a Low Voltage Low Power Current mirror based on body driven technique

This paper improved the output impedance of a Low Voltage Low Power (LVLP) current mirror by using body driven technique and transconductance enhancement. The applied technique increases the output impedance of current mirror significantly compared to other works. Also, it provides 0.5Ω and 6MHz improvement in input resistance and bandwidth, respectively. Operation principle of current mirror circuit with proposed improvement is discussed, the most important formulas are derived and the comparison between the performance of this circuit and the primary one is verified by simulation in TSMC 0.18µm CMOS technology. An output resistance of 39.5GΩ is achieved for the improved circuit that shows 5GΩ increment in comparison with primary circuit. Besides, simulation results show an input resistance of 12.8Ω and −3dB cut-off frequency of 216MHz for the improved current mirror circuit while it consumes only 42.5µW. Also, other specifications still remain unchanged. It should be noted that in this simulation, the power supply is 1V and the input current is 15µA.

A Physics-Based Circuit Aging Model for Mixed-Mode Degradation in SiGe HBTs

A physics-based silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) aging model for mixed-mode stress based on the lucky-electron model and reaction-diffusion theory is developed for integration with compact models. An effective aging parameter extraction method is described, and the aging model parameters are fit for a modern SiGe HBT platform. The aging model is implemented as a wrapper in the Cadence Spectre circuit simulator. Device-level aging simulations are shown to be well-matched to measured degradation data. The aging model is further used to explore the effects of aging on a simple current mirror circuit, showing a decrease in mirror ratio with degradation.