Minimum Supply Voltage Research Articles

A read-disturb-free stable low power and high-density GNRFET 6T SRAM with multi-VT technology

PurposeThe performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells.Design/methodology/approachThis study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue.FindingsThe GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart.Research limitations/implicationsNano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit.Practical implicationsGNRFET devices are suitable for implementing low power and high density SRAM cell.Social implicationsThe conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices.Originality/valueThis paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

A Novel Envelope Detector Based on Unipolar Metal-Oxide TFTs

The lack of an envelope detector (ED) hinders the realization of bidirectional communication between radio frequency identification (RFID)/near field communication (NFC) tags and readers in metal-oxide thin film transistor (TFT) technology. To solve this, we present a novel ED implementation based on unipolar metal-oxide TFTs. The ED is fully integrated by n-type TFTs and has a novel topology. It can detect an amplitude shift keying (ASK) signal with a minimum modulation depth of 15% and a maximum envelope rate of 8kbit/s, and its minimum supply voltage reaches 2.5 V. These characteristics are greatly improved compared with those of previous works based on complementary organic or hybrid organic/metal-oxide TFTs.

A 3.9 ppm/○C, 31.5 ppm/V ultra-low-power subthreshold CMOS-only voltage reference

This paper presents an ultra-low-power CMOS voltage reference based on the 0.18 μm standard CMOS technology. A temperature coefficient (TC) of 3.9 ppm/○ C without resistors or special devices is obtained by utilizing both the MOS transistor working in the deep triode region and the body bias technique. The current consumption in the minimum supply voltage of 0.85 V is as low as 96 nA. The line sensibility (LS) is 31.5 ppm/V when the supply voltage varies form 0.85 V to 3 V while the power supply rejection ration (PSRR) are −86.6 dB at 1 Hz and −50.2 dB at 100 Hz.

Low-Voltage 0.81mW, 1–32 CMOS VGA With 5% Bandwidth Variations and −38dB DC Rejection

A CMOS low-voltage amplifier with approximately constant bandwidth and DC rejection is introduced. The design is based on the cascade of a wide linear input range OTA, an op-amp and a servo-loop with extremely large time constants. It operates with ±0.45V supplies and a power consumption of 0.81mW in 180nm technology. The bandwidth changes only from 9.08MHz to 9.54MHz over a gain range from 1 to 32, it has a 9.8Hz low cutoff frequency and a DC attenuation of 38dBs. DC floating voltage sources are used to keep the gates of all differential pairs at a constant value close to a supply rail in order to operate the amplifier circuit with minimum supply voltage. The proposed circuit has small and large signal figures of merit FOM SS = 5380 (MHz*pF/mW) and FOM LS = 0.0085((V/ns)*pF/mA) for a nominal gain A = 32.

Fully Digital Rail-to-Rail OTA With Sub-1000-μm² Area, 250-mV Minimum Supply, and nW Power at 150-pF Load in 180 nm

A fully digital operational transconductance amplifier (DIGOTA) architecture for tightly energy-constrained low-cost systems is presented. A 180-nm DIGOTA testchip exhibits an area below the 1000- $\mu \text{m}^{2}$ wall, and 2.4-nW power under 150-pF load, and a minimum supply voltage ${V} _{\min }$ of 0.25 V. In the 0.3–0.5-V supply range, DIGOTA improves the area-normalized small (large) signal energy FoM by at least $836\times $ ( $267\times $ ) over prior sub-500-mV OTAs, while reducing area by $27\times $ – $85\times $ . The low- ${V} _{\min }$ and nW-power features are shown to enable direct harvesting at the mm-scale.

A 17.6-nW 35.7-ppm/°C Temperature Coefficient All-SVT-MOSFET Subthreshold Voltage Reference in Standard 0.18-μm N-Well CMOS

This paper presents a low-power, low-voltage, and low-temperature-coefficient (TC) MOSFET-only subthreshold voltage reference circuit based on a standard 0.18-μm n-well CMOS process. The circuit consists of two novel current generators and an I/V conversion circuit with temperature compensation. Under the control of a proposed pMOS-bulk-driven (PBD) temperature compensation circuit, two pMOSFETs operating in a linear region act as resistors with different TCs and can be used for PTAT and CTAT current generation. Owing to the PBD technique and the subthreshold operating method, these two current generators and the I/V conversion circuit can operate at low voltage. The proposed reference circuit is realized with only standard V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> (SVT) MOS devices. The measurement results show that it can operate at a minimum supply voltage of 0.5 V. The line sensitivity is 0.09% for supply voltages between 0.5 and 1.8 V. The PSRR measured at 100 Hz is 51.8 dB. A measurement of 20 samples indicates that the average TC is 35.7 ppm/°C across a temperature range of -40 to 85 °C. The proposed circuit consumes 17.6 nW from a 0.5-V power supply and occupies an active area of 0.0092 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Cryo-CMOS Digital Cell Library for Quantum Computing Applications

We present a digital cell library optimized for 4.2 K to create controllers that keep quantum processors coherent and entangled. The library, implemented on a standard 40-nm CMOS technology, was employed in the creation of the first 4.2 K RISC-V processor. It has achieved a minimum supply voltage of 590 mV, energy-delay product of 37 fJ/MHz, and maximum operating frequency of 740 MHz, all at 4.2 K in continuous operation. These results have been obtained from stand-alone characterization, successfully executing small C programs/benchmarks at 4.2 K. The overall performance of the library compares well against the state-of-the-art libraries designed for room temperature. In particular, we compared the performance of the proposed library against a foundry supplied library for the same process in several combinational benchmark circuits, showing significant improvements in power dissipation and frequency of operation.

A 48 pW, 0.34 V, 0.019%/V Line Sensitivity Self-Biased Subthreshold Voltage Reference With DIBL Effect Compensation

This paper presents a self-biased subthreshold CMOS voltage reference for low-power and low-voltage applications. To achieve near-zero line sensitivity and high PSRR, a compensation structure utilizing the drain-induced-barrier-lowering (DIBL) effect is proposed to sink a supply dependent current from the output branch of a self-biased CMOS reference, which cancels the bias current’s dependence on the supply voltage due to the DIBL effect. Fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology, the measurement results demonstrate that the proposed circuit could operate under a minimum supply voltage of 0.34 V and generate a reference voltage of 147 mV, while consuming only 48 pW power. The PSRRs measured at 1 Hz and 10 kHz are −70.6 dB and −50.2 dB, respectively. For 39 measured samples, the mean line sensitivity is 0.019%/V in a supply voltage range from 0.34 to 1.8 V, and the average temperature coefficients before and after trimming are 64.81 and 10.06 ppm/°C in 0 ~ 100 °C temperature range, respectively. The total area of the voltage reference circuit is 0.0332mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 1-nW Ultra-Low Voltage Subthreshold CMOS Voltage Reference With 0.0154%/V Line Sensitivity

This brief presents a CMOS voltage reference for Internet-of-Things applications, which requires ultra-low power and high insensitivity to voltage variation from ambient energy harvesting. This brief proposed a novel self-regulating circuit to significantly diminish the line sensitivity (LS) of reference voltage to supply voltage without using any amplifiers or passive components. All the transistors in this design work in subthreshold region for low voltage and low power operation. The proposed design is fabricated in a standard 0.18- $\mu \text{m}$ CMOS process. The measurement results show that, the proposed circuit could provide an average reference voltage of 151 mV with a variation coefficient of 0.84 %. It achieves a LS of 0.0154 %/V when the supply voltage varies from 0.5 V to 1.8 V. The measured power supply ripple rejections at 10 Hz, 1 kHz, 100 kHz, and 1 MHz are −73.0 dB, −49.4 dB, −49.6 dB, and −49.8 dB, respectively. The average temperature coefficient is measured as 89.83 ppm/°C with a standard deviation of 12.19 ppm/°C in a temperature range from −40 °C to +125 °C. The consumed power of this design is 1 nW with a minimum supply voltage of 0.4 V at room temperature, and the active area is 0.005 mm2.

Design of Class F Power Amplifier for 2.4ghz using Third Harmonics

Historically, travelling wave tube amplifier (TWTA) has been a common type of Microwave amplifier used commonly in terrestrial and space application due to their high efficiency and power handling capacity. However due to their bulky nature and also being very expensive, it is difficult to use them commercially in a large scale. Inspired by the advantage such as very less development cost, minimum supply voltage, gradual degradation and numerous commercial applications, Solid State Power Amplifier (SSPA) has been the replacement to vacuum tube Technology. The efficiency of the amplifier is one of the most important task in the microwave engineering research. An important figure of merit, power-added efficiency (PAE), is the main focus. Hence in this paper, class F Power amplifier is designed for 2.4GHz frequency. Class F Amplifier is also called as wave shaping amplifier since the harmonics generated helps the amplification process. The class f PA is biased nearer to the class B amplifier (close cut-off area) so the transistor can move back and forth rapidly to produce the harmonics. The efficiency of class F amplifier depends on how many harmonics are used for the amplification process. Here, the amplification process is performed up to the third harmonics which provides 41.606 dBm output power with 27dBm input power. Also a gain of more than 20.277dBm is achieved when the input given is 27dBm. Several other results like reflection Coefficient and transmission coefficient simulations has also been provided with the power added efficiency (PAE) of 75.402 achieved has also been simulated.

A 0.7-V 28-nW CMOS Subthreshold Voltage and Current Reference in One Simple Circuit

This paper presents a low-power and high-precision voltage and current reference (VCR) in one simple circuit. The voltage reference is derived from the threshold voltage difference between an I/O (i.e., 3.3-V NMOS) and standard (i.e., 1.8-V NMOS) transistors with temperature-independent bias current, and the current reference is the voltage reference divided by a temperature-insensitive resistor. The resistor is made up by series connection of a proportional-to-absolute-temperature (PTAT) NWELL resistor and a complementary-to-absolute-temperature (CTAT) high-resistance poly resistor in series. Implemented in a standard 0.18- $\mu \text{m}$ CMOS process, the proposed VCR circuit takes an active area of only 0.055 mm2. The measured voltage and current references ( $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ ) at room temperature are 368 mV and 9.77 nA, respectively. The measured average temperature coefficient (TC) of $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ are 43.1 ppm/°C and 149.8 ppm/°C over a temperature range of −40~125°C with one-time trimming and the variation coefficients are 0.35% and 1.6%, respectively. The measured voltage and current line sensitivities are 0.027%/V and 0.6%/V, respectively. The minimum supply voltage is 0.7 V with a total power consumption of 28 nW. The measured power supply ripple rejection (PSRR) of $\text{V}_{\mathrm {ref}}$ is −65 dB @DC and −39.4 dB at frequencies higher than 1 Hz.

A 8.2-pW 2.4-pA Current Reference Operating at 0.5 V With No Amplifiers or Resistors

This brief presents an ultra-low-power (ULP) current reference circuit based on $V_{th}$ (threshold voltage), which consumes pico-watt of power under 0.5V supply voltage. Compared to traditional current references based on threshold voltage, this design uses no amplifier, thus friendly scaling and simple structure are achieved simultaneously. In order to save area, the huge resistor is replaced by a gate-leakage MOS transistor. The proposed circuit is designed in a 40nm CMOS process. The minimum supply voltage is 0.5V. Post simulation results show that the power consumption is only 8.2pW at 0.5V $V_{DD}$ at room temperature. According to our knowledge, this is the smallest power consumption compared to prior works, thanks to its simple structure. Under process + mismatch Monte-Carlo simulations, the temperature coefficient after trimming is 18.6ppm/°C over 0°C to 85°C. The core area is only 0.00025mm2 in layout. Apart from the 40nm process, this circuit is also designed in a 130nm process to demonstrate the robustness under different processes.

PARAMETERS OF COEFFICIENTS OF THE RAIL FOUR-POLE OF THE JOIN THE JOINTLESS RAIL CIRCUI TLESS RAIL CIRCUIT ACCORDING T CCORDING TO LOCOMOTIVE RECEIVER

In article questions of a conclusion of the coefficients of the equations of a rail four-polar of a jointless rail circuit are considered, taking into account uncertainty of borders where the travelling receiver which is applied now on a railway transportation is used. Mathematical modeling of four-pole coefficients by locomotive receiver is given. Analytical expressions and coefficients for calculation of the locomotive current flowing under the receiving coils and transfer resistance are derived. The scheme of a jointless rail circuit in the presence of moving units and mutual influence on each other is given. The influence of the carrier information from the traffic light in front, where it is necessary to take into account the factor of the signal level from the outgoing train, so that the information of the neighboring rail circuit would not be perceived, since there are no insulating joints. A scheme with five four poles has been developed and coefficients of these four poles have been obtained to calculate the current of the locomotive flowing under the receiving coils. Analytical expressions are obtained for determining the current for receiving by the receiving coils of a locomotive, the minimum supply voltage of an unbroken rail circuit and the transmission resistance of a rail circuit in normal operation for a locomotive receiver.

Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time

A self-timed pulsed latch (STPL) is proposed for low $V_{\mathrm {DD}}$ operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The measurement results from the test chip fabricated in the 65-nm technology proves that the hold time is reduced by 77% and the minimum operating supply voltage is lowered by 300 mV compared with the conventional pulsed latch. In addition, the measurement results show that the STPL can reduce the sequential overhead, because the STPL is free from setup time issue from which the conventional master–slave-based flip-flop (MSFF) suffers. The simulation results show that the input-to-output delay of STPL, which also determines the sequential overhead, is smaller by 45% in 0.6 V compared with that of the MSFF structure.

A Low Power Low Supply MOS-Only Subthreshold Voltage Reference for Wide Temperature Range

A Sub-1V, MOS-only Voltage Reference Circuit (VRC) has been proposed with the utmost of transistors working as subthreshold region for low-supply and low-power applications. A supply-insensitive current is passed to Active Load Circuit (ALC) for supply and temperature independence at the output reference voltage. It has four current mirrors connected in a closed loop configuration to generate a supply-independent current which is passed through the ALC resulting supply and temperature insensitive output reference voltage. The ALC has a combination of two subthreshold NMOS transistors having different threshold voltages. The presented VRC is simulated using standard 90 nm CMOS model for 0.25-1 V supply voltage range. The simulation result gives minimum operating voltage required as 0.25 V for which all transistors work in their respective region of operation. For the supply range of 0.25-1 V, the obtained mean voltage reference is 100.4 mV with the line regulation of 0.186 mV/V. The temperature coefficient (TC) of 51ppm/°C is achieved for a wide temperature range of -50 to 135°C with the given minimal operating supply voltage. The power dissipation for minimal supply voltage at room temperature is 33 nW. The proposed VRC exhibits a high PSRR of -52.5 dB at 100Hz and -29 dB at 1 MHz.

A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering

This brief presents ultra low-voltage CML D-latch and D-Flip-Flop (DFF) topologies in deeply scaled CMOS technologies, able to operate at a supply voltage as low as 0.5 V (no other CML DFFs are able to operate at such a low supply voltage). The topology is based on a modified version of the Folded D-Latch, recently proposed by the authors. In this brief a detailed analysis on the minimum supply voltage allowed by the proposed topologies and a comparison with the one of the other low voltage topologies is also included. Post layout Simulations referring to a commercial 28 nm CMOS process and schematic level simulations adopting 14 nm predictive technology models are provided. They show the heavy advantages of the improved Folded DFF with respect to the state of the art.

Measurement and Simulation of On-Chip Supply Noise Induced by System-Level ESD

On-chip supply noise induced by power-on ESD is studied with the aid of on-chip monitor circuits and circuit simulation. The monitor circuits’ outputs provide information about the magnitudes of the ESD-induced supply noise. The supply noise monitor circuits were implemented on a 130-nm CMOS test chip. Voltage monitor circuits record the maximum and minimum supply voltage excursions. Flip-flop monitor circuits respond to a rapid voltage change at the supply. Circuit simulation is used to validate hypotheses about how the noise spreads throughout the power delivery network.

A 0.5-V-supply, 37.8-nW, 17.6-ppm/°C switched-capacitor bandgap reference with second-order curvature compensation

This paper presents a switched-capacitor (SC) bandgap reference (BGR) with second-order curvature compensation for ultra-low power systems. The gate-source voltage of a sub-threshold MOSFET is proposed to implement the second-order curvature compensation voltage in this work. And then, a SC network is used, not only to add the second-order voltage and the first-order one together, but also to fulfill the summing weight effectively and precisely. In this way, the silicon area and power consumption can be reduced simultaneously. Furthermore, the design methodology of summing weight is investigated, and thus the temperature coefficient (TC) can be significantly reduced. The proposed SC-BGR was implemented and simulated in a CMOS 0.18 μm process, the average output voltage is 426.1 mV, achieving a TC of 17.6 ppm/°C from −20 to 100 °C under a 0.5 V minimum supply voltage. With the help of the SC architecture, a small chip area of 0.0975 mm2 is achieved with only 37.8-nW power consumption.

A Low-Power, Sub-1-V All-MOSFET Subthreshold Voltage Reference Using Body Biasing

A low-voltage and low-power all-MOSFET voltage reference is presented having most of the transistors working in subthreshold region. The basic beta-multiplier with cascode transistor provides a supply-independent current utilized by the active load circuit to generate an output reference voltage using body biasing. The proposed circuit is simulated using standard SCL 180-nm CMOS technology for the supply voltage ranging from 0.75[Formula: see text]V to 1.8[Formula: see text]V. The simulation obtains an average output voltage reference of 450.4[Formula: see text]mV for the given supply range at room temperature. The minimum power dissipation at room temperature is 54.37[Formula: see text]nW. The temperature coefficient (TC) of 28.13[Formula: see text]ppm/∘C is achieved having the temperature range of [Formula: see text]10–87∘C for the minimum operating supply voltage. It has the PSRR values of [Formula: see text]39.4[Formula: see text]dB at 100[Formula: see text]Hz and [Formula: see text]12[Formula: see text]dB at 1[Formula: see text]MHz. Also, the active area of the proposed circuit is 0.014[Formula: see text]mm2.

A Low Voltage Bandgap Current Reference with Low Dependence on Process, Power Supply, and Temperature

The minimum power supply voltage of a typical bandgap current reference (BGCR) is limited by operating temperature and input common mode range (ICMR) of a feedback amplifier. A new BGCR using a bandgap voltage generator (BGVG) is proposed to minimize the effect of temperature, supply voltage, and process variation. The BGVG is designed with proportional to absolute temperature (PTAT) characteristic, and a feedback amplifier is designed with weak-inversion transistors for low voltage operation. It is verified with a 0.18-㎛ CMOS process with five corners for MOS transistors and three corners for BJTs. The proposed circuit is superior to other reported current references under temperature variation from -40℃ to 120℃ and power supply variation from 1.2 V to 1.8 V. The total power consumption is 126 ㎼ under the conditions that the power supply voltage is 1.2 V, the output current is 10 ㎂, and the operating temperature is 20℃.