Minimum Leakage Current Research Articles

Exploring the Relationship Between Electrical Characteristics and Changes in Chemical Composition and Structure of OSG Low-K Films Under Thermal Annealing

The influence of annealing temperature on the chemical, structural, and electrophysical properties of porous OSG low-k films containing terminal methyl groups was investigated. The films were deposited via spin coating, followed by drying at 200 °C and annealing at temperatures ranging from 350 °C to 900 °C. In the temperature range of 350–450 °C, thermal degradation of surfactants occurs along with the formation of a silicon-oxygen framework, which is accompanied by an increase in pore radius from 1.2 nm to 1.5 nm. At 600–700 °C, complete destruction of methyl groups occurs, leading to the development of micropores. FTIR spectroscopy reveals that after annealing at 700 °C, the concentration of silanol groups and water reaches its maximum. By 900 °C, open porosity is no longer observed, and the film resembles dense SiO2. JV measurements show that the film annealed at 450 °C exhibits minimal leakage currents, approximately 5 × 10−11 A/cm2 at 700 kV/cm. This can be attributed to the near-complete removal of surfactant residues and non-condensed silanols, along with non-critical thermal degradation of methyl groups. Leakage current models obtained at various annealing temperatures suggest that the predominant charge carrier transfer mechanism is Poole–Frenkel emission.

Single-crystalline High-κ GdOCl dielectric for two-dimensional field-effect transistors

Two-dimensional (2D) dielectrics, integrated with high-mobility semiconductors, show great promise to overcome the scaling limits in miniaturized integrated circuits. However, the 2D dielectrics explored to date still face the challenges of low crystallinity, diminished dielectric constant, and the lack of effective synthesis methods. Here, we report the controllable synthesis of ultra-thin gadolinium oxychloride (GdOCl) nanosheets via a chloride hydrate-assisted chemical vapor deposition (CVD) method. The resultant GdOCl nanosheets display good dielectric properties, including a high dielectric constant (high-κ) of 15.3, robust breakdown field strengths (Ebd) exceeding 9.9 MV/cm, and minimal gate leakage currents of approximately 10−6 A/cm2. The top-gated GdOCl/MoS2 field-effect transistors (FETs) exhibit commendable switch characteristics, a negligible hysteresis of ~5 mV and a subthreshold swing down to 67.9 mV dec−1. The GdOCl/MoS2 FETs can also be employed to construct functional logic gates. Our study underscores the significant potential of the 2D GdOCl dielectric for innovative high-speed operated nanoelectronic devices.

Performance of Organic Electrochemical Transistors with Ionic Liquid Crystal Elastomers as Solid Electrolytes.

Organic electrochemical transistors (OECTs) have emerged as attractive devices for bioelectronics, wearable electronics, soft robotics, and energy storage devices. The electrolyte, being a fundamental component of OECTs, plays a crucial role in their performance. Recently, it has been demonstrated that ionic liquid crystal elastomers (iLCEs) can be used as a solid electrolyte for OECTs. Their capabilities, however, have only been shown for relatively large size substrate-free OECTs. Here, we study the influence of the different alignments of iLCEs on steady state and transient behavior of OECTs using a lateral geometry with source, drain, and gate in the same plane. We achieve excellent electrical response with an ON/OFF switching ratio of >105 and minimal leakage current. The normalized maximum transconductance gm/w of the most sensitive iLCE was found to be 33 S m-1, which is one of the highest among all solid-state-based OECTs reported so far. Additionally, iLCEs show high stability and can be removed and reattached multiple times to the same OECT device without decreasing performance.

A novel approach to obtain superior microwave absorption using Non-Conducting polymer jacket coated Multi-Layer Hexaferrite-TMDC nanocomposite film

This article represents the imposing electromagnetic interference (EMI) shielding behaviour of non-conducting polymer jacket-coated Co2Y-hexaferrite-MoS2 binary nanofillers incorporated PVDF multi-layer nanocomposite films. The presence of Co2Y-hexaferrite inside PVDF enhanced the magnetic permeability, whereas the incorporation of semiconducting transition metal dichalcogenide (TMDC), MoS2, inside the PVDF matrix improves the polarization effects of the nanocomposite films. The crystalline phases corresponding to Co2Y-hexaferrite, MoS2 nanoparticles and the multi-phase nanocomposite films have been justified using XRD analysis and Rietveld refinement study. FESEM micrographs confirm the hexagonal and cotton-ball structures of Co2Y-hexaferrite and MoS2 nanoparticles, respectively; in addition, the presence of Co2Y-MoS2 binary nanofillers inside the PVDF matrix has been confirmed. The stability of the nanocomposite films against electrical breakdown is clearly demonstrated by the minimum leakage current observed at 90 kV/m under J-E characteristics. The room temperature maximum magnetization of 33.32 emu/g of Co2Y-hexaferrite at an external magnetic field of 50,000 Oe helps in incurring magnetic losses and the corresponding improvement of shielding effectiveness due to absorption (SEA) of the nanocomposite films. This article demonstrates the modulation of SEA of the nanocomposite films depending on both the binary nanofillers loading percentage inside PVDF and the thickness of the nanocomposite films. Also, a unique mechanism corresponding to the coating of a non-conducting polymer jacket over a multi-layer structure has been opted herein to improve SEA in the frequency range of 12–18 GHz. This unique mechanism demonstrates that the maximum SEA for the non-conducting polymer jacket-coated multi-layer nanocomposite film is −51.23 dB at 14.03 GHz, and the corresponding total shielding effectiveness (SET) is −74.51 dB at 13.23 GHz, along with > 99.9999 % attenuation.

Effect of modulating monovalent ion doped on A-site high-entropy perovskites

High-entropy materials constitute solid solutions composed of five or more elements. This complex and diverse composition endows the materials with unique physical and chemical properties, presenting immeasurable value in material design. Despite such potential applications, the composition design still has deficiencies, and the influence mechanism of elements remains a research gap. In this work, a series of new high-entropy perovskites (La0.5X0.5)0.2(Ce0.5X0.5)0.2Ba0.2Sr0.2Ca0.2TiO3 (where X = Li, Na, K) were designed and synthesized. We systematically studied their phase structures, microscopic morphologies, as well as dielectric and ferroelectric properties. Notably, novel findings are reported. Specifically, (La0.5Li0.5)0.2(Ce0.5Li0.5)0.2Ba0.2Sr0.2Ca0.2TiO3 ceramics exhibit excellent breakdown field strength (Eb = 135 kV cm−1) and minimal leakage currents in 10−7–10−6 A cm−2. Moreover, the designed ceramics display exceptional dielectric constant (εr = 5 × 104) and saturation polarization (Ps = 2.8 μC cm−2) properties. These findings introduce novel insights into designing high-entropy ceramic components, enabling the customization of new dielectric and ferroelectric properties by manipulating doped monovalent ions.

Effect of rapid thermal annealing on DC performance of Mg0.30Zn0.70O/Cd0.15Zn0.85O MOSHFET

This study focuses on a cost-effective method for fabrication of a metal oxide semiconductor-heterostructure field effect transistor (MOSHFET) based on MgZnO/CdZnO (MCO) using dual ion beam sputtering (DIBS), in contrast to the more expensive epitaxial growth system. The MOSHFETs developed in this research exhibit notable characteristics, such as a substantial two-dimensional electron gas (2DEG) transconductance (∼2.6 mS), a high ION/IOFF response ratio in the order of 108, and minimal gate leakage current. Furthermore, we explore the impact of rapid thermal annealing (RTA) on the drain current at various temperatures (600 °C and 800 °C). The results indicate a fourfold improvement in drain current compared to unannealed conditions, primarily attributed to reduced contact resistance and no degradation in term of MgZnO/CdZnO structure. Additionally, an analysis of post-RTA treatment under a nitrogen (N2) atmosphere on gate leakage current is presented. The investigation spans temperatures ranging from 400 °C to 800 °C, revealing that above 600 °C (gate leakage at 400 °C–600 °C is around ∼10−9 A), gate leakage in HFET is augmented by one order of magnitude (∼10−8 A) due to a phase change in the dielectric. These findings underscore the feasibility of DIBS-grown MCO MOSHFETs as an economical solution for the mass production of switching devices and sensors.

Van der Waals Epitaxial Growth of Ultrathin Indium Antimonide on Arbitrary Substrates through Low-Thermal Budget.

III-V semiconductors possess high mobility, high frequency response, and detection sensitivity, making them potentially attractive for beyond-silicon electronics applications. However, the traditional heteroepitaxy of III-V semiconductors is impeded by a significant lattice mismatch and the necessity for extreme vacuum and high temperature conditions, thereby impeding their in situ compatibility with flexible substrates and silicon-based circuits. In this study, a novel approach is presented for fabricating ultrathin InSb single-crystal nanosheets on arbitrary substrates with a thickness as thin as 2.4nm using low-thermal-budget van der Waals (vdW) epitaxy through chemical vapor deposition (CVD). In particular, in situ growth has been successfully achieved on both silicon-based substrates and flexible polyimide (PI) substrates. Notably, the growth temperature required for InSb nanosheets (240°C) is significantly lower than that employed in back-end-of-line processes (400°C). The field effect transistor devices based on fabricated ultrathin InSb nanosheets exhibit ultra-high on-off ratio exceeding 108 and demonstrate minimal gate leakage currents. Furthermore, these ultrathin InSb nanosheets display p-type characteristics with hole mobilities reaching up to 203 cm2 V-1 s-1 at room temperatures. This study paves the way for achieving heterogeneous integration of III-V semiconductors and facilitating their application in flexible electronics.

Data-driven optimization for microgrid control under distributed energy resource variability

The integration of renewable energy resources into the smart grids improves the system resilience, provide sustainable demand-generation balance, and produces clean electricity with minimal leakage currents. However, the renewable sources are intermittent in nature. Therefore, it is necessary to develop scheduling strategy to optimise hybrid PV-wind-controllable distributed generator based Microgrids in grid-connected and stand-alone modes of operation. In this manuscript, a priority-based cost optimization function is developed to show the relative significance of one cost component over another for the optimal operation of the Microgrid. The uncertainties associated with various intermittent parameters in Microgrid have also been introduced in the proposed scheduling methodology. The objective function includes the operating cost of CDGs, the emission cost associated with CDGs, the battery cost, the cost of grid energy exchange, and the cost associated with load shedding. A penalty function is also incorporated in the cost function for violations of any constraints. Multiple scenarios are generated using Monte Carlo simulation to model uncertain parameters of Microgrid (MG). These scenarios consist of the worst as well as the best possible cases, reflecting the microgrid’s real-time operation. Furthermore, these scenarios are reduced by using a k-means clustering algorithm. The reduced procedures for uncertain parameters will be used to obtain the minimum cost of MG with the help of an optimisation algorithm. In this work, a meta-heuristic approach, grey wolf optimisation (GWO), is used to minimize the developed cost optimisation function of MG. The standard LV Microgrid CIGRE test network is used to validate the proposed methodology. Results are obtained for different cases by considering different priorities to the sub-objectives using GWO algorithm. The obtained results are compared with the results of Jaya and PSO (particle swarm optimization) algorithms to validate the efficacy of the GWO method for the proposed optimization problem.

Cylindrical hot cathode ionisation gauge – Construction and testing

Hot cathode ionisation gauges are indispensable in measuring high and ultra-high vacuum. In the present work the construction details and the metrological evaluation of a novel gauge design — the cylindrical ionisation gauge is presented. With the aim of enhancing accuracy and stability both in the short and long term, details of the mechanical assembling of electrodes and precautions to minimize leakage currents influencing ion current measurement are described. Performance evaluations demonstrate high short-term stability, with linearity error, reproducibility, and repeatability values consistently below 1 %, placing the gauge at the same level as the most stable ionisation gauges. Operating across a pressure range of at least 6 orders of magnitude, the gauge exhibits low linearity error from high to ultra-high vacuum ranges. Its capability to measure pressures below 10−9 mbar remains open and requires further investigation.

Ultra-high performance hafnium-based capacitors: Synergistic achievement of high dielectric constant and low leakage current

The relationship between the dielectric constant and leakage current of materials often exhibits a negative correlation. However, to sustain Moore's Law, the semiconductor industry necessitates novel materials that simultaneously possess a high dielectric constant and low leakage current, meeting the shrinking demands of electronic components. In this study, a high-performance hafnium-based thin film capacitor achieved through the collaborative effects of bottom electrode engineering and ion doping. Tungsten (W) as the bottom electrode, with its chemically inert nature and low thermal expansion coefficient, proves advantageous in improving interface quality and promoting the generation of the high-k phase in HfO2. Concurrently, yttrium (Y) ion doping contributes to stabilizing the high-k phase of HfO2, reducing non-lattice oxygen, and enhancing the disorderliness of the dielectric thin film. By synergistically integrating these factors, the hafnium-based thin film capacitor achieves a high dielectric constant of 36.6 while maintaining minimal leakage current (Electric field ∼ 6 MV/cm, J ∼ 10−8 A/cm2) and a high charge storage capacity (Urec ∼ 104.4 J/cm³). These research findings open a promising pathway for the development of novel hafnium-based materials with broad applicability and exceptional dielectric performance.

2-D Si0.8Ge0.2 source double-gate pocket PTFET for low power application: Modeling and simulation

To process 1-bit of information the small supply voltage (Vdd) and minimal leakage current are needed for transistors. Subthreshold swing (SS) of 60 mV/dec at 300 K is the basic bottleneck in metal oxide semiconductor field effect transistors. DFT in QuantumATK R-2020.09 was used to study Si0.8Ge0.2 band structure and band gap. A p-type tunnel field effect transistor (PTFET) was modeled employing the dual gate concept. Top gate has two metals; source and counter doped pocket are Si0.8Ge0.2. According to the proposed device simulation, the proposed device is showing excellent thermal stability for large on-current (Ion), weak off-current (Ioff), and weak ambipolar current (Iambi) at different temperatures. The proposed device achieves the Ion of 72.44 µA/µm and 3.2 µA/µm at supply voltage of −1 V and −0.5 V, respectively. At −0.5 V of Vdd, current ratio of Ion/Ioff is more than 1012, so device can be used for low power applications.

Transition of Cu film to Cu2O film through oxygen plasma treatment

Metal–oxide-semiconductor-based thin-film transistors have attracted increasing research attention owing to their wide bandgap and minimal leakage current. However, the prevalent n-type behavior of several oxide semiconductors prompted the exploration of p-type alternatives. Among these, Cu films are promising candidates for different fields. In this study, the effectiveness of oxygen plasma treatment for the transition of Cu films to their p-type oxide semiconductor phase, i.e., Cu2O, was demonstrated with a focus on low-temperature fabrication for future integration in flexible devices. We reported the adjustability of the oxidation depth of a Cu thin film and the effect of oxidation dynamics by controlling the bottom radio frequency power of a high-density plasma system. This novel approach enabled metal-to-semiconductor transitions and modulation of the physical properties of Cu2O thin films by inducing changes in their composition and microstrain. The oxidation dynamics, oxidation depth, crystallinity, and film surface were analyzed. Moreover, the changes in the optical bandgap were determined, with the transition of the Cu (111) phase to the Cu2O (111) phase confirmed as a function of the process time. As oxidation progressed, particles formed on the surface of the Cu2O thin film and the particle size increased. Further, the oxidized Cu thin film was determined to be Cu2O rather than CuO. Therefore, oxygen plasma treatment is expected to be a new approach to low-temperature oxidation.

Stress effect on the leakage current distribution of ferroelectric Al0.7Sc0.3N across the wafer

This study presents an investigation into the stress effect on the leakage current in ferroelectric Al0.7Sc0.3N films by experiments and density functional theory (DFT) computations. The experiments are based on 8-in. 100 nm Al0.7Sc0.3N films obtained from pulsed DC co-sputter deposition technology, which exhibit non-uniform compressive in-plane stress across the wafers and similar distributions of leakage current, suggesting close dependence between each other. DFT computations revealed that stress affects leakage current in two ways: the level of traps introduced by nitrogen vacancy and the formation energy of nitrogen vacancy in Al0.7Sc0.3N. By considering both factors, the leakage current of Al0.7Sc0.3N films increases with larger compressive in-plane stress, as observed in the experimental results. Additionally, the DFT calculation results indicated that the leakage current is more sensitive to compressive stress compared to the tensile, and the minimum leakage current can be obtained with neutral in-plane stress. These findings provide a guideline for stress engineering to optimize the AlScN-based ferroelectric devices.

Electrical and Mechanical Behavior of Aerosol Jet–Printed Gold on Alumina Substrate for High‐Temperature Applications

There is a growing interest in the development of microelectronics that can perform reliably and robustly at temperatures above 300 °C. Such devices require stable thermal properties, low thermal drift, and thermal cycling resistance. Conventional hybrid circuit technology demonstrates high‐temperature packages, but the high costs and lead time are significant drawbacks. In contrast, additive manufacturing processes, including aerosol jet printing (AJP), offer cost and time benefits, as well as 3D structures and embedded features. However, the properties and reliability of additive packaging materials at extreme temperatures are not well known. Herein, the reliability at temperatures up to 750 °C in terms of electrical performance and mechanical strength of aerosol jet printed gold thick films onto ceramic substrates are assessed. Thermal coefficient of resistance of printed gold films is measured. The electrical resistance stability and leakage current of printed gold structures are also characterized during over 100 h of aging at temperatures up to 750 °C. Finally, the mechanical adhesion strength of the printed gold films is evaluated after aging for 100 h at temperatures up to 750 °C. The adhesion of the printed gold to the ceramic substrates remains high after aging, very stable resistances and minimal leakage currents have been observed.

Fine‐Tuning the Molecular Design for High‐Performance Molecular Diodes Based on Pyridyl Isomers

AbstractBetter control of molecule‐electrode coupling (Γ) to minimize leakage current is an effective method to optimize the functionality of molecular diodes. Herein we embedded 5 isomers of phenypyridyl derivatives, each with an N atom placed at a different position, in two electrodes to fine‐tune Γ between self‐assembled monolayers (SAMs) and the top electrode of EGaIn (eutectic Ga−In terminating in Ga2O3). Combined with electrical tunnelling results, characterizations of electronic structures, single‐level model fittings, and DFT calculations, we found that the values of Γ of SAMs formed by these isomers could be regulated by nearly 10 times, thereby contributing to the leakage current changing over about two orders of magnitude and switching the isomers from resistors to diodes with a rectification ratio (r+=|J(+1.5 V)/J(−1.5 V)|) exceeding 200. We demonstrated that the N atom placement can be chemically engineered to tune the resistive and rectifying properties of the molecular junctions, making it possible to convert molecular resistors into rectifiers. Our study provides fundamental insights into the role of isomerism in molecular electronics and offers a new avenue for designing functional molecular devices.

Fine-Tuning the Molecular Design for High-Performance Molecular Diodes Based on Pyridyl Isomers.

Better control of molecule-electrode coupling (Γ) to minimize leakage current is an effective method to optimize the functionality of molecular diodes. Herein we embedded 5 isomers of phenypyridyl derivatives, each with an N atom placed at a different position, in two electrodes to fine-tune Γ between self-assembled monolayers (SAMs) and the top electrode of EGaIn (eutectic Ga-In terminating in Ga2 O3 ). Combined with electrical tunnelling results, characterizations of electronic structures, single-level model fittings, and DFT calculations, we found that the values of Γ of SAMs formed by these isomers could be regulated by nearly 10 times, thereby contributing to the leakage current changing over about two orders of magnitude and switching the isomers from resistors to diodes with a rectification ratio (r+ =|J(+1.5 V)/J(-1.5 V)|) exceeding 200. We demonstrated that the N atom placement can be chemically engineered to tune the resistive and rectifying properties of the molecular junctions, making it possible to convert molecular resistors into rectifiers. Our study provides fundamental insights into the role of isomerism in molecular electronics and offers a new avenue for designing functional molecular devices.

H9 and H10 Transformer-Less Solar Photovoltaic Inverters for Leakage Current Suppression and Harmonic Current Reduction

Now-a-days, transformer-less inverters integrating renewable energy resources as solar photovoltaic systems are commonly employed in many grid-connected distributed energy systems in both industrial and residential settings. Transformer-less photovoltaic (TLPV) inverters have attracted increased attention due to their unique advantages, such as increased efficiency, low cost, and ease of installation. Converting fluctuating solar dc power to consistent ac power has been a difficulty in the recent decade to avoid security risks like ground fault currents and leakage currents. Leakage current minimization is one of the most crucial factors in the TLPV inverters. Different TLPV inverter topologies have been presented in the past, with leakage current being reduced by galvanic isolation on the dc or ac side of the inverter, common mode voltage (CMV) clamping, and modulation techniques. This paper proposed two novel single-phase grid-tied TLPV inverter topologies with control blocks, which can handle a wide variety of grid voltages. The proposed TLPV inverters offer very small leakage current, reduced total harmonic distortion (THD), and improved power quality. Based on the number of semiconductor devices, the proposed inverters are termed as H9 and H10 inverters. The switches are controlled using the unipolar sinusoidal pulse width modulation, which results in constant common mode voltage and reduction in leakage currents to 11.09 and 11.73 mA for the proposed H9 and H10 inverters, respectively. The proposed H9 and H10 inverters minimize the THDs to 1.62 and 2.09%, respectively. Besides, the proposed H9 and H10 inverters exhibit 98.19 and 98.12% European efficiency. The simulations are carried out on MATLAB/Simulink and the results are experimentally validated using downscale laboratory test platforms

Design and Performance Analysis of 32 × 32 Memory Array SRAM for Low-Power Applications

Computer memory comprises temporarily or permanently stored data and instructions, which are utilized in electronic digital computers. The opposite of serial access memory is Random Access Memory (RAM), where the memory is accessed immediately for both reading and writing operations. There has been a vast technological improvement, which has led to tremendous information on the amount of complexity that can be designed on a single chip. Small feature sizes, low power requirements, low costs, and great performance have emerged as the essential attributes of any electronic component. Designers have been forced into the sub-micron realm for all these reasons, which places the leakage characteristics front and centre. Many electrical parts, especially digital ones, are made to store data, emphasising the need for memory. The largest factor in the power consumption of SRAM is the leakage current. In this article, a 1 KB memory array was created using CMOS technology and a supply voltage of 0.6 volts employing a 1-bit 6T SRAM cell. We developed this SRAM with a 1-bit, 32- × 1-bit, and 32 × 32 configuration. The array structure was implemented using a 6T SRAM cell with a minimum leakage current of 18.65 pA and an average delay of 19 ns. The array structure was implemented using a 6T SRAM cell with a power consumption of 48.22 μW and 385 μW for read and write operations. The proposed 32 × 32 memory array SRAM performed better than the existing 8T SRAM and 7T SRAM in terms of power consumption for read and write operations. Using the Cadence Virtuoso tool (Version IC6.1.8-64b.500.14) and 22 nm technology, the functionality of a 1 KB SRAM array was verified.

Dual Boost Five-Level Switched-Capacitor Inverter With Common Ground

This brief presents a five-level common ground type (5L-CGT) inverter topology with double voltage boosting. This topology uses only eight switches, two capacitors that can be charged equal to the input source. The advantageous feature of this topology is the CGT configuration between the input source and output load, which ensures minimal common-mode voltage and leakage current. A detailed analysis is done to select and size capacitors, along with quasi-soft charging to minimize the charging current ripples across the capacitors. The performance of the proposed 5L-CGT inverter is tested for inductive load, varying the modulation index/load/input voltage under experimental test conditions. A detailed comparison is done with the existing state-of-art that shows the merits of the proposed topology in terms of equal voltage stress across the capacitor with voltage boost. The power loss analysis for the inverter is carried out using PLECS with efficiency to be 97.20%, and the experimental efficiency is found to be 96.54% for the 900W inverter prototype.

Performance Analysis of Various Fin Patterns of Hybrid Tunnel FET

High speed and low power dissipation devices are expected from future generation technology of Nano-electronic devices. Tunnel field effect transistor (TFET) technology is unique to the prominent devices in low power applications. To minimize leakage currents, the tunnel switching technology of TFETs is superior to conventional MOS FETs. The gate coverage area of different fin shape hybrid tunnel field-effect transistors is more impacted on electric characteristics of drive current, leakage current and subthreshold slope. In this paper design various fin patterns of hybrid TFET devices and shows on better performance as compared with other fin shape hybrid tunnel FET. The TCAD simulation tool is used to determine the characteristics of different fin shape tunnel FET.