Microprogrammed Control Unit Research Articles

Erratum: New approach to synthesis of self-checking microprogrammed control units with specified fault-detection probabilities

Erratum: New approach to synthesis of self-checking microprogrammed control units with specified fault-detection probabilities

Erratum: Concurrent self-checking for microprogrammed control units: an analytical survey

Erratum: Concurrent self-checking for microprogrammed control units: an analytical survey

Concurrent self-checking for microprogrammed control units: an analytical survey

A comparative survey and systematic categorisation of the main western and soviet publications over the past five years in the area of concurrent techniques for control-flow checking for microprocessor-based systems is presented. The types of faults encountered in microprogram execution are described, and a number of techniques for detecting these faults are outlined. These include methods for partitioning the control flow-graph to allow checking, and methods for forming and transforming vertex check keys. A number of algorithms are presented, together with examples of architectures for self-checking microprogrammed control units, and a discussion of their engineering implementation.

New approach to synthesis of self-checking microprogrammed control units with specified fault-detection probabilities

The paper presents an initial attempt to create a general procedure for synthesising concurrent self-checking microprogrammed control units having a prescribed quality of checking. We consider systems in which diagnostic features are provided by the use of a checking strategy based on special check keys to code the flow graph representing the microinstruction sequence. We investigate the conditions under which the diagnostic features allow faulty transitions in the flow graph to be successfully detected, and derive a method for obtaining probabilistic estimates of faulty transition detection. We present a matrix description of the probabilities of the events involved: fault occurrence at flow graph vertices, faulty transitions between vertices, and the detection of faulty transitions. We include a simple example illustrating the methodology, in which a proposed scheme is first analysed to determine its performance, then modified to meet a higher specification.

Tolerance to transient faults in microprogrammed control units

The detection of and recovery from transient faults that cause errors in microprogrammed control units are addressed. Error detection is based upon a particular form of signature analysis, namely the run-time computation of a value (the signature) that depends strictly on the microprogram path (the sequence) under execution. The microprogram is statistically segmented (sequences are defined in a fixed way, at design time), and an anticipated signature is associated with each sequence. At run time, at the start of each sequence the computation of the signature is restarted, whereas at the end the computed signature is compared with the anticipated signature of the sequence. If the check is passed, the status of the control unit is saved in suitable registers, and the previously saved status is discarded. If the check fails, the last-saved status is restored (rolled back) and microprogram execution restarts from this last-saved point. >

Design methodology and microdiagnostics development for a self-checking microprocessor

The conventional design of electronic circuits is intolerant to operational faults. Self-checking logic is aimed at online fault detection and can hence be incorporated to achieve reliable operation. In this paper, the design of a self-checking microprocessor is discussed. Self-checking strategies for different functional units are selectively and judiciously applied, and also modified wherever necessary, for the design of the register section, the arithmetic & logic unit and the control unit. A self-checking microprogrammed control unit, capable of supporting normal instruction execution concurrently with diagnostics, is developed. The design methodology has been applied to Intel's 8085A microprocessor as a case study to make it self-testing. Overheads involved have also been estimated.

Standalone microsequencer

A microsequencer lies at the heart of any microprogrammed control unit, being responsible for stepping through the microinstructions of a microprogram. Until recently, microprogrammed control units were implemented either by large quantities of TTL logic and a ROM or by more modest amounts of TTL logic, a ROM and a few bit-slice devices. The Altera EPS444/448 standalone microsequencer contains all the logic needed to implement a microsequencer on a single chip. Inside the device there is a microprogram sequencer, branch control logic, a microprogram return address stack, a microprogram memory and a user programmable microcode EPROM that holds the microprogram to be executed. This single device, when programmed, provides the functionality of a custom IC without the time or expense of designing one. The EPS444 and EPS448 have relatively short microinstruction outputs (12 bit and 16 bit respectively) that are intended for high-performance controller designs, but they may also be used for simple microcoded control units. The EPS444/448 offers an ideal solution to the design of a synchronous state machine. Synchronous state machines are attractive alternatives to microprocessors where simplicity, speed, performance and economics are more important than the versatility of microprocessors. This application note, taken from the Altera EPS444/448 data sheet, describes the operation of this sequencer and its instruction set.

Designing for concurrent error detection in VLSI: application to a microprogram control unit

An integrated approach to the design of a microprogram control unit (MCU) that possesses the distinction of having comprehensive concurrent-error-detection (CED) capability for errors generated by VLSI physical failures is presented. The implementation of the functionally complex single-chip MCU is discussed and the fault model used is explained. Circuit design techniques that have recently been developed for self-checking VLSI systems are introduced. The first critical appraisal based on actual mask-level layouts of custom CED design versus error detection through duplication and comparison, are also presented.

A design methodology of microprogrammed controllers for custom CMOS IC's

This paper presents a design methodology for microprogrammed control units of full Custom CMOS integrated circuits. The proposed multiple language interpretation levels (instructions, microinstructions and nanoinstructions) provide a fast and structured way to realize an area-efficient controller from the specifications to the geometrical layout. A 20th order programmable FIR filter will, as an example, illustrate the methodology.

Concurrently totally self-checking microprogram control unit with duplication of microprogram sequencer

This paper presents a new design method for concurrently Totally Self-Checking Microprogram Control Units of bit-slice microprocessors. We consider a fault model that includes arbitrary failures in a single IC package and multiple errors on address, data and control buses. In our method the microprogram sequencer and the remaining functional units that support it are duplicated. Also, the microinstructions with their b-bit addresses are encoded in a distance-2 n-adjacent encoding scheme. Finally an N-adjacent code checker is employed to monitor the outputs from the microprogram memory and the microprogram sequencer. The checker and hence the whole Microprogram Control Unit becomes concurrently Totally Self-Checking by using a small number of microinstructions stored in predefined addresses in the microprogram memory. Our method in comparison to others has the added advantage to detect concurrently not only the permanent faults, but also temporary faults occurring during normal operation.

Application of signature analysis to the concurrent test of microprogrammed control units

In this paper, an architecture for a microprogrammable processor with built-in test is described. A novel approach in handling the transactions between the blocks of a microprogram for self-test is presented. The approach uses signature analysis to test the control section independent of the data section. A fault model for a microprogrammed control unit is proposed. The effects of the errors that are caused by these faults are analyzed. Effectiveness of signature analysis with respect to these errors is studied with the use of Berlekamp's algorithm. As a result, structure of the signature register that provides the best coverage is determined.

A customized control store design in microprogrammed control units

The paper reports on the control store cost minimization using an approach related to the bit reduction method. A methodology is presented for finding the microinstruction format which provides a minimum joint cost of the control store and microinstruction decoder circuitry for a given set of microprograms. The optimization criterion measures the area taken by the control store and decoders in a large scale integrated circuit. The methodology is based on the concepts of codable microoperation classes and microoperation class distributivity introduced in the paper. The codable classes are those that provide the length reduction of the microinstruction field used for binary encoding microoperation combinations, compared to the single bit/microoperation encoding method. Microoperation class properties and basic types of fields assignments in microinstruction word formats for codable class approach are also discussed.

A microprogrammable architecture with quasi time-transparent structured control

The paper is concerned with efficient implementation of evolved modular and structured microprogramming. A microprogrammable architecture is presented that permits designing hierarchical complicated modular microprograms at two distinct levels: the global control and the data processing level. The architecture is based on two cooperating microprogram control units that separately store and perform control and executive microinstructions and microcode modules. The control organization of an implementing computer is presented which assures the quasi time-transparency of modular control in microprograms during the microprogram execution. This is achieved by parallel functioning of constituent control units, that permits preparing in advance addresses of executive modules referenced by control microinstructions. The efficient implementation of control statements of high level languages and microprogramming at the assembler language level for the proposed architecture are also discussed in the paper.

Concurrent Fault Detection in Microprogrammed Control Units

This paper specifies procedures for defining a monitor circuit that can detect faults in microprogram sequencers. The monitor and the sequencer operate in parallel and errors are detected by comparing outputs from the monitor circuit with outputs from the sequencer. Faults that cause errors in the flow of control are detectable, as well as some faults that cause errors only in the microinstruction fields. The design procedure presented for monitors consists of four parts. First, a model of the program flow is constructed that only retains the information required to define a monitor. Second, faults in a specified fault set are modeled by the errors they cause in the program flow model. Third, the functional requirements of the monitor are specified in terms of partitions on the states of the program flow model. Fourth, the logic design of the monitor is completed.

SNAP: A VLSI architecture for artificial intelligence processing

The organization and operation of a semantic network array processor (SNAP) are described. The architecture consists of an array of identical cells each containing a content addressable memory, microprogram control, and communication unit. Each cell is dedicated to one node of the semantic network and its associated relations. The array can perform global associative functions under the supervision of an outside controller. In addition, each-cell is equipped with the necessary logic to perform individual functions. A set of primitive instructions was carefully chosen. Some of the applications discussed include pattern search operations, production systems, and inferences. A LISP simulator was developed for this architecture, and some simulation results are presented.

MASCO

The design of a host machine architecture for implementing an existing image machine architecture is considered. The proposed microarchitecture uses a microprogrammed control unit to emulate the Motorola MC6809 microprocessor architecture. The detailed hardware characteristics of the proposed machine are described and the microinstruction set is defined. The microroutines that emulate the MC6809 instruction set have been developed. A practical implementation using current technology is studied and some realistic timing characteristics are determined. The simulation of the proposed architecture is reviewed and the performance is evaluated. Finally, comparisons with existing models are made and the results are discussed.

An alternative approach towards the design of control units

In this communication the individual advantages of both the hardwired and the microprogrammed control units have been exploited to suggest a hybrid approach for the decoding of instructions. The method is simple and straightforward. It retains the fast speed as well as the flexibility aspects. Furthermore, timing analysis has been carried out to justify the effectiveness of the proposed approach.

A design approach for a microprogrammed control unit with built in self test

We present an architecture for concurrent testing of a microprogrammed control unit. This approach is compared with other control unit testing strategies. The advantages of this approach are: a) it allows testing of the control unit independent of the operational section, b) minimizes the hardcore, c) it is easily incorporated in microprogrammed control units, d) since it is concurrent, probability of detecting intertermittent errors is high, e) it is incorporated into the specification and therefore amenable for VLSI implementations.

Design of concurrently testable microprogrammed control units

Four schemes for the design of concurrently testable microprogrammed control units are presented. In Schemes 1 and 2 the concept of path signatures is used for detection of malfunctions in the control unit. Two different methods for computation of signatures are given. In Schemes 3 and 4, a check-symbol is assigned to each microinstruction and the integrity of these check-symbols is checked concurrently. A deterministic approach is used for generation of check-symbols in Scheme 4. A comparative study of these schemes is done with respect to storage and time overhead, error coverage, and implementation complexity.

Dynamic Testing of Control Units

The goal of the paper is to propose test methods for wired or microprogrammed control units without special test facilities: no special access path, i.e., no direct and exhaustive observation means. Consequently, the control unit will be tested through the current control algorithms under "normal" sequencing facilities and through the controlled operative part; the proposed methodology consists of choosing an adequate set of algorithms and specific data, allowing an efficient test with respect to errors hypothesis.