Abstract
An integrated approach to the design of a microprogram control unit (MCU) that possesses the distinction of having comprehensive concurrent-error-detection (CED) capability for errors generated by VLSI physical failures is presented. The implementation of the functionally complex single-chip MCU is discussed and the fault model used is explained. Circuit design techniques that have recently been developed for self-checking VLSI systems are introduced. The first critical appraisal based on actual mask-level layouts of custom CED design versus error detection through duplication and comparison, are also presented.
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