Micron Technology Research Articles

A Design of Image Acquisition System Based on FPGA and USB2.0

The paper introduces a realization method of high-speed image acquisition system based on FPGA and USB2.0. After introducing the CMOS chip MT9T001 of Micron Technology, Inc. and the universal interface chip CY7C68013 of Cypress Semiconductor Corporation, we design the hardware platform of image acquisition system and the control program written by Verilog HDL language through which FPGA can simulate I2C bus to configure CMOS. Then we introduce the development of firmware, driver and application of the USB interface. This paper completed the design and the experiment of image acquisition system well. In the test, the system achieves the requirement of real-time display. The collected images are clear, which can satisfy design requests.

Design and Implementation of class AB VGA in deep sub micron technology

Design and Implementation of class AB VGA in deep sub micron technology

Numerical analysis of direct current circuits containing bipolar and metal oxide semiconductor transistors

SUMMARYThe paper brings a numerical method for finding multiple DC operating points of circuits containing bipolar and metal oxide semiconductor (MOS) transistors fabricated in micrometer technology. The method is based on the concept of separable Newton homotopy and division of the searching space into currently changed rectangles (boxes). The method traces a piecewise‐linear homotopy path and intersects some specific plane at the points corresponding to the operating points. Numerical experiments show that the method is remarkably efficient. Three examples including bipolar junction transistors and metal oxide semiconductor circuits are given. Copyright © 2014 John Wiley & Sons, Ltd.

Effects of micronization on micromeritics properties of baicalin

Baicalin extremely fine powder was made by using ball-mill and the effect of micronization on the micromeritics properties of baicalin was studied and analyzed. The microstructures of baicalin ordinary and extremely fine powder were compared by scanning electron microscope, differential scanning calorimeter and X-ray diffraction and the powder characteristic of them was investigated. The hygroscopicity was studied. The effect of micronization on the dissolution of baicalin was investigated. The results showed that the chemical constituents of baicalin were not changed after micronization with better compressibility. It was confirmed that micronization technology had a certain application value in promoting the insoluble component of baicalin absorption with higher dissolution.

Does internal communication to generate trust always increase commitment?

Purpose– The aim of this paper is to investigate the relationship between employee trust towards the company and their commitment to it. For this reason, this study questioned if certain levels of trust presented in each department at Micron Technology Italy were interrelated with the levels of commitment.Design/methodology/approach– A survey at Micron Technology Italy was conducted. Of the 1,580 employees who received the questionnaire, 892 responses were collected, resulting in a 56.46 per cent response rate.Findings– The research findings show that for departments where trust values are below 6.8, the commitment level follows the trust value: there is a positive relation between these two factors. However, departments where employee trust reaches values higher than 6.8 are not reciprocated by a proportional commitment level that tends to reach a “satisfaction point”.Research limitations/implications– The results are only partially coherent with previous studies. Further research is needed to determine whether these reports hold true under different situations/companies.Practical implications– Since commitment does not seem to be continuously increasing, after a certain point it is not cost-effective for the company to implement communication strategies aimed at increasing employee trust in a non-targeted way. The need for customized communication strategies emerges as does the importance of understanding internal communication as integrated with other human resource management levers.Originality/value– This paper offers an original contribution to the ongoing discussion concerning employee engagement. Employees' trust does not always lead to employee commitment behaviors inside the organization.

Operational Transresistance Amplifier Using Submicron Technology

Operational Transresistance Amplifier is important active element in Analog integrated circuits and system. The OTRA is receiving increasing attention as a basic building block in analog circuit design. It is relatively a new building block operating from low voltage supplies and overcomes the finite gain bandwidth product associated with traditional op-amp. The basic principle behind the design of OTRA is to provide amplification of high frequency signals with the using standard operational amplifier. In this work effort is made to study the role of OTRA as an active building block in analog circuits. Various CMOS realization of OTRA present in the literature are studied and these circuits are used to realize various signal processing and generating circuits. Based upon component sensitivity tendency and variation amount, just properly adjusting one or two resistances by a small difference, or giving approximate component values for achieving precise output responses is investigated and developed different OTRA realization. In many applications high speed and efficient power consumption is required is desired. For this purpose conventional transistor technique are usually chosen, but this results in lower power efficiency. So, the different sub- micron technologies are used. A sub-micron system integrates millions and millions of Electronic components in a small area .The main objective behind the use of this technology is to make the analog and digital system as compact as possible and more power efficient with the required functionality of OTRA and VLSI. The Low Power is the key contribution of the main processing blocks in OTRA system.

Power Analysis and Synthesis of BIST Technique on UART

The increasing growth of sub – micron technology has resulted in shrinking of the device size leading to increase in device density. In the modern System-on-a-Chip (SoC) design, many cores are integrated into a single chip, some of them are embedded. This increases the functional complexity of the chip. The internal sub – circuits of the chip cannot be accessed directly from the primary inputs of the chips. So the testing of the chip is becoming very time consuming and costly. Such SoC designs make the test of these embedded cores become a great challenge. Thus Automatic Testing Equipments (ATE) is becoming costly process for testing. To reduce the cost of testing the chips, Built in Self Test (BIST) has emerged as an cheaper alternative. BIST is a design technique that allows the chip to test itself. In this paper, the BIST is implemented on UART using Verilog. The simulation and synthesis of the design are performed using ModelSim SE PLUS 6.5 simulator and XILINX ISE 14.5 synthesis tool.

Effect of micronization technology on physicochemical and antioxidant properties of dietary fiber from buckwheat hulls

Buckwheat is at present considered a food component of high nutritional value. In order to study the effect of buckwheat hull dietary fiber (DF) particle size on its functional and antioxidant properties, buckwheat hull DF was ground by ultrafine grinding and its particle size was determined using laser diffraction method. The results showed that ultrafine grinding technology could efficiently pulverize the DF particles to submicron scale, particle size distribution was close to a Gaussian distribution, and soluble DF content increased. With particle size decrease, the water holding capacity (WHC), water retention capacity (WRC), swelling capacity, oil binding capacity (OBC) and nitrite ion absorption capacity were significantly (p<0.05) increased. Micronized insoluble DF showed increased total phenolic content (TPC), 2,2'-azinobis(3-ethylbenzothiozoline-6-sulfonic acid) diammonium salt (ABTS), 1,1-diphenyl-2-picrylhydrazyl (DPPH) radical scavenging activity and ferric reducing antioxidant power (FRAP). Positive correlations were detected between ABTS, DPPH, FRAP and TPC. A modification method was obtained to yield a kind of health beneficial DF with higher soluble DF content, WHC, WRC, swelling capacity, OBC, nitrite ion absorption capacity and antioxidant activity. This study could be useful for the application of buckwheat and related products in the food industry.

Prototypes for components of a control system for the ATLAS pixel detector at the HL-LHC

In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled, which will increase the accelerators luminosity by a factor of 10. In the context of this upgrade, the inner detector of the ATLAS experiment will be replaced entirely including the pixel detector. This new pixel detector requires a specific control system which complies with the strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University of Wuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS Chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4x4 DCS Chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub micron technology. We present results from measurements from new prototypes of components for the DCS network.

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

Tree driven mesh is gaining popularity as a viable method to distribute clock with minimum skew in Deep Sub Micron (DSM) technology. In the design of the leaf level mesh, the density of the mesh at various parts of the chip is a crucial factor which decides the clock skew and power dissipated in the mesh. We propose a capacitance driven mesh formation methodology which forms a minimum wire length, non-uniform mesh when compared to the traditional skewdriven mesh. After connecting the sinks to the mesh by a combination of Steiner tree and stubs, appropriately sized buffers are placed at optimal locations such that skew and power dissipation are minimized. When our algorithms were tested on ISPD2010 benchmarks, the power dissipated in the mesh was found to be 25% lesser and the skew was 32% to 45% lesser than the skew driven mesh.

Table of Contents

Abstract NEWS Study: More resources needed for performance assessments Microsoft commits $500 million to global youth initiative SCUTTLEBUTT SPOTLIGHT Computer industry Micron Technology Inc. Advanced Micro Devices Inc. Adobe Systems Inc. Citrix Systems Inc. Aerospace industry Alliant Techsystems Inc. Lockheed Martin Corp. Airbus S.A.S. Bombardier Inc. GRANT ALERTS Aging American Federation for Aging Research's grants Aging‐related mid‐career research grants Children and Youth Liberty Mutual's Responsible Sports grants Education School library humanities program grants National School Library Program of the Year Award School science technology awards Environment SeaWorld and Busch Gardens Conservation Fund National Forest Foundation's Matching Awards Program Health Care American Psychological Foundation grants Burroughs Wellcome Fund's Preterm Birth Initiative Religion Center of Theological Inquiry's dissertation fellowships

UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2

The increased leakage, yield inefficiency, process, power supply, and temperature variations have significant aftereffects on the performance of complex VLSI architectures especially if mapped on ultra deep sub micrometer (UDSM) technologies. In this paper we assess the technology trend based on three industrial technologies (90, 65, and 45 nm) using a state of the art processor as benchmark: The UltraSparc Niagara 2 from SUN Microsystem. We analyze frequency, dynamic, and static power and area after synthesis varying power supply voltage and temperature. We then compare these exhaustive analyses of system level performance as a function of technology to ITRS device level estimations. The results suggest that this prediction can be of help when addressing both the technological scaling and the variability scenario of the selected technology. We believe that correctly predicting specific values on performance variations when realistic conditions and technologies are changed could provide a valuable information for the architect. Our analysis advises the designer on the effective applicability of the ITRS trends to system performance, but also pinpoints that a reliable system level prediction should better take into account the design complexity.

The Evolution of Knowledge Spillover and Company cluster in Semiconductor Industry

Because of technology-driven and capital intensive characters of the semiconductor industry, it is significant but arduous for most companies to proceed by themselves with technology development and innovation. It is clear that innovation can be regarded as an interactive process, which requires collaborative relationships among different agents of the processes. Thus, the goal of this study is to scrutinize and characterize the dynamic evolution of involuntary knowledge spillover (patent citations among assignees) and voluntary knowledge spillover (assignees as joint owners/co-assignees) in this industry. By using Unite States patents divided into three periods (six-inch, eight-inch and twelve-inch microchips), the researchers of this study have discovered that the patent growth of this industry has been significant over the period of time from 1997 to 2004. The “Core Actor” included seven assignees with higher knowledge in/out flows in both the eight and twelve inch periods, such as enterprises of AMD, IBM, INTEL, MICRON TECHNOLOGY, SAMSUNG ELECTRONICS, TSMC TAIWAN, TOSHIBA. Among eleven assignee clusters across eight and twelve inch periods formed by co-assignees with the voluntary knowledge spillover, there were nine clusters, which were all Japan assignees, suggesting a closer relationships existing in the field of this industry in Japan.

Modeling of Human Voice Box in VLSI for Low Power Biomedical Applications

Communication is heavily dependent on ideas expressed through speech. The ideas and tonal qualities during vocal expression give voice an idea about person characteristics and personality. The estimation of vocal tract configuration from speech sound to represent speech events with robust and compact signals that describe the salient features of speech is an important area of speech communication. The Human Voice Box (Glottis) is the source of voice production and an important part of human body. Recent techniques of speech processing, such as speech recognition and speech synthesis, use the glottal closure and opening instants. Current models of the glottal waves derive their shape from approximate information rather than from exactly measured data. In this work, an electrical model of Human Voice Box is presented by exploiting fluid volume velocity to current and fluid pressure to voltage. The glottis modeled as current source includes linear and nonlinear impedances to represent laminar and turbulent flow, respectively, in the vocal tract. The complete model of glottis runs at power supply of 1.8 volt and the design is verified in a standard TSMC 0.18 micrometer technology on BSIM 3v3 model using ELDO Simulator.

Effects of Scaling in SEE and TID Response of High Density NAND Flash Memories

Heavy ion single-event effect (SEE) measurements and total ionizing dose (TID) response for Micron Technology single-level cell 1, 2, 4, 8 Gb commercial NAND flash memory and multi-level cell 8, 16, 32 Gb are reported. The heavy ion measurements were extended down to LET 0.1 MeV-cm2/mg. Scaling effects in SEE and TID response are discussed. Floating gate bit error upset cross section does not scale with feature size at high LETs, except for single-level cell 8 Gb device which is built with 51 nm processes. The threshold LET does not change with scaling. Charge pump TID degradation and standby current improves with scaling. In general, the effect of radiation is either unchanged or is less severe for highly scaled NAND flash memories.

Albumin/Gentamicin Microspheres Produced by Supercritical Assisted Atomization: Optimization of Size, Drug Loading and Release

In this work, the supercritical assisted atomization (SAA) is proposed, for the first time, not only as a micronization technology but also as a thermal coagulation process for the production of bovine serum albumin (BSA) microspheres charged with Gentamicin sulfate (GS). Particularly, different water solutions of BSA/GS were processed by SAA to produce protein microspheres with different size and antibiotic content. SAA precipitation temperature was selected in the range 100-130 °C to generate protein coagulation and to recover micronized BSA in form of hydrophobic aggregates; GS loading was varied between 10% and 50% (w/w) with an encapsulation efficiency which often reached 100%. In all cases, spherical and noncoalescing particles were successfully produced with a mean particle size of 2 µm and with a standard deviation of about ±1 µm. The microspheres also showed a good stability and constant water content after 60 days of storage. The release profiles of the entrapped drug were monitored using Franz cells to evaluate the possible application of the produced microspheres in wound dressing formulations. Particularly, the microspheres with a BSA/GS ratio of 4:1 after the first burst effect (of 40% of GS loaded) were able to release the GS continuously over 10 days.

A High-Swing OTA with wide Linearity for design of self-tunable linear resistor

Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.

Design of a Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.

Design of A Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.

Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband Platform

MIMO-OFDM systems aim to improve transmission quality and/or throughput but require significant signal processing capability and flexibility at reasonable cost. This paper proposes a reconfigurable architecture and associated algorithm optimizations for these types of systems based on the IEEE 802.11n and IEEE 802.16e standards. In particular, we describe the implementation of two key computations onto this architecture, namely Fast Fourier Transform (FFT) and Space-Time Block Decoding (STBD). The design is post-layout using a UMC 0.18micron technology at a clock rate of 100MHz. Performance comparisons with other optimization methods and hardware implementations are given.