Power Analysis and Synthesis of BIST Technique on UART

Abstract

The increasing growth of sub – micron technology has resulted in shrinking of the device size leading to increase in device density. In the modern System-on-a-Chip (SoC) design, many cores are integrated into a single chip, some of them are embedded. This increases the functional complexity of the chip. The internal sub – circuits of the chip cannot be accessed directly from the primary inputs of the chips. So the testing of the chip is becoming very time consuming and costly. Such SoC designs make the test of these embedded cores become a great challenge. Thus Automatic Testing Equipments (ATE) is becoming costly process for testing. To reduce the cost of testing the chips, Built in Self Test (BIST) has emerged as an cheaper alternative. BIST is a design technique that allows the chip to test itself. In this paper, the BIST is implemented on UART using Verilog. The simulation and synthesis of the design are performed using ModelSim SE PLUS 6.5 simulator and XILINX ISE 14.5 synthesis tool.