Micrometers Design Rule Research Articles

Architecture of A High Performance LED Printhead Platform

Océ's continuous feed printer families are developed to satisfy the ever increasing speed and quality requirements of our customers. One of the key components for higher performance in electrophotographic printing is the exposure system. Océ develops and manufactures LED printheads since many years because of their high reliability and durability. A third generation printhead platform was developed to meet highest speed and quality requirements while lowering overall cost. This was achieved by a combination of mechanical, optical, and electronical improvements.For the mechanical part, customization of a general-purpose pick-and-place system ensured a three-sigma LED-to-LED placement accuracy of less than two microns.The selection of a very uniform SelfocTM lens array with high aperture but low depth of focus forced a mechanical design with minimized tolerances between LED and photoconductor surface in order to achieve optimum print resolution.LED drivers were implemented in full custom mixed-signal CMOS technology with .35 micron design rules. An on-chip bus for data, clock, status, and control signals makes the array length scalable to arbitrary print width with minimal changes to parts. The sustained data throughput of the driver chain comes close to 2 gigabits per second. Various power and timing control settings can be configured via bus commands. Each chip autonomously performs redundancy checks to alert the controller in case of data integrity errors. Non-uniformities of light output are compensated for by individual energy calibration for each dot. Bi-level, four-level, and sixteen-level exposure modes are available. All exposure functions are controlled digitally to achieve highest precision and reliability.Thermal management utilizes a massive heat sink onto which the heat-dissipating elements are directly bonded, and a liquid cooling system to provide for uniform temperature inside each individual print head and across all print heads of a printing system.

Applications of High Resolution Immersion Lens Scanning Electron Microscopes to Sem-Based Defect Review at 250nm Design Rules

IntroductionThe use of SEM-based defect review tools has increased dramatically over the past five years as the semiconductor industry moved from 0.7 micron to 0.25 micron design rules. During this period, a dramatic inflection occurred at the 0.5 micron node; optical microscopy lacked sufficient resolution to determine even if a simple etch step was properly performed. Accordingly, many “inspection SEMs” were introduced into the wafer fabrication facility. With ever increasing focus on yield improvement, defect review SEM's proliferated in the fab in an effort to drive down both baseline defects and process excursions. In order for such an effort to be successful, a clear improvement in the low voltage image resolution performance of the scanning electron microscope was required. Commercial vendors have responded with impressive tools achieving image resolutions of 2.5–4nm @1 kV. At this level of performance, routine observation of semiconductor wafers is possible at 100,000X magnification. This dramatic improvement in resolution is the result of many factors, by far the biggest of which is the use of “immersion lens” designs which employ a strongly excited objective lens operated at short working distances (∼2mm). This electron optic design was first introduced into the laboratory SEM market, with instruments capable of producing approximately 1.2nm resolution at 20kV. These high performance lenses in which the magnetic field extends below the bottom of the polepiece, were fitted onto 200mm platforms allowing whole wafer inspection/defect review. The features of such tools and their application to the IC industry is the subject of this paper. An example of the superb imaging performance of such a 200mm tool is illustrated in figure 1.

Evaluation of Double Spacer Local Oxidation of Silicon (LOCOS) Isolation Process for Sub-Quarter Micron Design Rule

Double Spacer local oxidation of silicon (LOCOS) with shallow recess of silicon (DS-LOCOS) is described. The process has two spacers, a thin nitride spacer and a medium temperature chemical vapor deposition (CVD) oxide spacer. The process does not have intentional silicon recess etching step but achieves the shallow recess of silicon through nitride overetchings. It has been found that the key processes of the DS-LOCOS are both isolation etching and spacer etching, which critically affect 2ΔW and V t roll-off behaviors of active transistor and junction characteristics. The DS-LOCOS achieves physical bird's beak length of below 0.03 µ m/side, field oxide volume ratio over 80%, and superior planar surface. The DS-LOCOS also gives no degradation in punchthrough voltage down to 0.20 µ m isolation spacing and in gate oxide reliability. These results show that the DS-LOCOS is a simple and promising isolation technology for sub-quarter micron design rule.

Anomalous Field‐Oxide‐Ungrowth Phenomenon in Recessed Local Oxidation of Silicon Isolation Structure

An anomalous field‐oxide‐growth phenomenon in a recessed local oxidation of silicon (LOCOS) structure with a nitride spacer (R‐LOCOS), in which the field oxide growth at the center of the opening area is suppressed when isolation spacing is small, is reported. The field‐oxide‐ungrowth (FOU) phenomenon was found to have strong structural dependence, on the aspect ratio of the opening area, active pattern density, and silicon recess depth. By changing process conditions, such as dry etching and wet cleaning conditions, however, the FOU was not affected. Since the tendency of the FOU occurrence was coincident with that of the microloading effect in reactive ion etching, the FOU was believed to originate from a residue on the exposed silicon surface after the etching process. When silicon was not recessed, the FOU was not observed at any of the structural variations. From a two‐dimensional simulation of field oxidation, it has been found that in a nonrecessed LOCOS structure, a residue on the silicon surface does not significantly affect field oxide growth, but in the recessed LOCOS structure, field oxide growth is very sensitive to the existence of a residue on the recessed surface. Thus, to successfully use the recessed LOCOS structure with a subquarter micron design rule avoiding the occurrence of the FOU, structural factors that include an active pattern layout should be carefully chosen.

High Temperature Local Oxidation of Silicon Field Isolation Morphological Characterization

The morphological characterization of local oxidation of silicon (LOCOS) isolation has been carried out by using steam oxidation in the temperature range 1050 to 1180°C and as‐grown field oxide thickness between 150 and 600 nm. A bird's beak minimum is observed between 100 and 1140°C, corresponding to a change in the bird's beak growth mechanism from a diffusion type to a regime dependent on silicon surface oxidation and nitride oxidation rates. For the first time on LOCOS isolation, the improvement of field oxide thinning by reducing field oxide thickness is reported: that enables a possible scaling for subquarter micrometer design rules.

Neural networks application for fast, direct correction kernel generation for proximity effeccts correction in Electron Beam Lithography

Fast, direct correction kernel generation by neural network application was shown. Estimation of the proximity effects by experimental method is used. Neural processor consists of two dedicated neural networks. Training set for Network 1 is based on convolutional Fourier pre compensation method with optimal filtering over the test structure MAT1. Second step of correction - ORG mode - made by Network 2 is a multivariable function approximation in which exact weight vector for arbitrary chosen technological parameters - proximity parameters - in prepared for actual corrector - CORR - mode of Network 2. Learned in such way neural processor is ready to correct for any patterns for any proximity function in almost real time. Modelled comparison of analytical correction method for real sub-quarter micrometer design rules chip with proposed here assure shortening of the process from 6 years to 17 hours. Some further improvements of the hardware solutions of the neural processor are also suggested.

Rapid Thermal Processing-Manufacturing Perspective

AbstractWhile repeatable and accurate measurement of temperature in rapid thermal processing (RTP) remains a subject of ongoing research, inception of large-diameter wafers and deep subhalf micron design rules may be viewed as good news for implementing RTP during the development phase for later transfer to volume manufacturing. To date, the only well-established application of RTP in manufacturing is silicide annealing. However, research during the past decade has demonstrated the feasibility of using RTP to replace essentially all furnace-based thermal processes in sub-half micron process flows. These developments in the RTP capability offer several technological and economic benefits such as improved defect control, higher product yields, and faster development cycles for DRAM-type technologies at a reduced cost and with an earlier entry of the driver products during the revenue-generating period.In this paper, we review several applications of RTP such as silicide anneals, borophosphosilicate glass (BPSG) reflow, dopant activation, and rapid thermal nitridation (RTN) and discuss the integration issues related to advanced process flows. Furthermore, we highlight important manufacturing parameters like throughput, machine cost and uptime, software and hardware issues, wafer dimensional analysis, and simulation expectations. While considering volume manufacturing, we make some calibration and process control recommendations.

Comparison of advanced plasma sources for etching applications. IV. Plasma induced damage in a helicon and a multipole electron cyclotron resonance source

The effect of plasma induced damage on device yields becomes increasingly crucial as gate oxide thicknesses approach the 50–70 Å range for quarter micron design rules. To quantify plasma induced damage for new low pressure, high density plasma sources, inductively coupled carrier lifetime and photoluminescence are measured. Also, UV-visible spectroscopic ellipsometry is used to closely examine the wafer surface both during and after plasma exposure. This study is part of an ongoing research program that compares the etching performance of two commercially available, advanced plasma sources: a Lucas Labs helicon and a Wavemat multipole electron cyclotron resonance source. For n-type and p-type, nominally 100 μs lifetime wafers, plasma exposure in both sources under optimum polysilicon overetch conditions results in a degradation of carrier lifetimes of less than 5% for unprotected versus oxide protected crystalline silicon. For wafers with an initial carrier lifetime of 400 μs, exposure to plasmas in both sources leads to a decrease in carrier lifetimes to approximately 345 μs. The decrease in carrier lifetime, although measurable, is at least an order of magnitude smaller than measured in conventional reactive ion etching (RIE) processes. To simulate an RIE etching process, rf-bias power is applied without source power so that both sources behave like highly asymmetric, parallel plate RIE reactors with the wafer platen acting as a driven electrode and the source wall acting as a grounded electrode. Under these conditions carrier lifetimes below 45 μs were measured in both sources with wafers that had initial lifetimes of 400 μs. Photoluminescence measurements indicate incorporation of hydrogen into the etched material, but no formation of interstitial defects associated with plasma induced damage. For samples exposed to a plasma at 25 and 50 W rf-bias, hydrogen produced from HBr dissociation readily incorporates into the sample. Exposure to a plasma at 200 W applied rf-bias results in a decrease in carrier lifetime and an increase in hydrogen incorporation. Under high rf-bias conditions, hydrogen incorporation is probably aided by ion surface damage. Ultraviolet-visible ellipsometry does not detect any morphological damage induced in silicon wafers, but as with carrier lifetime and photoluminescence measurements, significant damage is detected after exposure to rf-bias power without applied source power. Ellipsometry also detects a difference between real-time and post process spectra after HBr and Cl2 plasma exposure corresponding to the desorption of a film approximately 12 Å thick. This is not observed after Ar plasma exposure. Instead, the roughened surface remains stable which shows that the differences observed during and after plasma exposure for HBr and Cl2 are indeed the result of a chemically reacting layer.

A Strategic Optical Lithography for Below 0.25 Micron Design Rules.

Semiconductor device fabrication costs are dramatically escalating each year. Almost lithographers suffer from a paradox; Which lithography will best meet the technical and economic needs of VLSI manufacturing in the drive toward below 0.25 micron design rules?. This paper gives an outline of the possibility and strategy of optical lithography with productivity and cost efficiency for the development and production of 0.25micron design rule devices and beyond on the basis of our recent development results.To control costs, lithography will continue to push the extension of optical lithography as far as it can go. In the lithography for 256MbDRAMs production, a capability of 0.20micron lithography resolution is required. We have developed a new chemically amplified positive resist with high stability and an excimer laser based stepper with high alignment accuracy and off-axis illumination for KrF excimer laser lithography as a state-of-the art on shorter wavelength. The solution of 256MbDRAMs lithography is a complementary strategy employing both i-line for non-critical layers and KrF excimer laser for critical layers in order to achieve the lowest manufacturing cost.Sub-quarter micron feature size is required to lithography for the development of 1Gbit DRAMS. In order to break-through below 0.20micron barrier of optical lithography, ArF excimer laser lithography, which is a super state-of-the-art, has been challenged and developed. The challenges are constructed of the projection system installing a refractive achromatic aspherical 4X lens and a suitable resist material with high transparency. It is expected not only as the next significant technology but also as the final optical lithography to produce next generation VLSI. The strategy of optical lithography will be a endless development for semiconductor industries.

Infrared-measurement of X-ray mask heating during sr-lithography

For the fabrication of ULSI circuits, it is necessary to master sub-half micron design rules, which include an efficient patterning procedure and critical dimensions related overlay requirements. In addition to the alignment accuracy, the overlay budget is determined by the pattern placement precision on X-ray masks. There are two kinds of absorber pattern displacements — those having static and others having dynamic causes. Static displacements are produced by e-beam patterning or during mask fabrication; dynamic distortions can be induced for example by temperature variations. This paper presents experimental results on the temperature rise of X-ray masks in synchrotron radiation lithography. We used an in-situ thermographic system to determine the temperature distribution during the exposure.

A synchrotron compatible production oriented x-ray stepper

A second generation X-ray stepper is described, based on work performed at the Institute for Microstructure Technology in Berlin. The equipment presents specifications suitable for the production of sub-half micron design rule ULSI circuits with high throughput.

Computer-aided design of an eight bit binary counter N-MOS chip for large scale integration (LSI)

An integrated eight bit synchronous binary counter along with input/output circuits: gate protection, two phase clock, pad-out has been designed for MOS LSI. The counter has a master-slave flip-flop and a combinational logic to generate the next state, and outgoing carry outputs from this stage. The combination logic has been implemented using pass transistors and thus acts as a steering type logic. This type of logic is very fast, consumes lesser power and needs significantly less area for its implementation. Latest CAD techniques: interactive Graphics system of Applicon AGS/860 LSI Design Station, MOS circuit simulation program MSINC and Design Rule Check (DRC) program have been used for design and chip layout. The entire chip has been laid out in the area of 3 × 3 mm 2 including test devices and structures for testability analysis. The design is based on LOCOS N-MOS (E-D) technology and 8 micron design rules. The Electromask pattern generation (PG) tape has been prepared from Applicon for making chrome masks. A set of six masks have been used for the fabrication of device and die encapsulated in dual-in line package and tested for its performance. Counter works up to 5 MHz clock frequency as expected from design calculations. From 25 stage ring oscillator frequency measurement the gate delay comes out to be 6 nS. The counter design could easily be substituted as a sub-system/building block or cell in any MOS LSI system design where it makes a part of it.

A Radiation-Hard Silicon Gate Bulk CMOS Cell Family

A radiation-hardened silicon gate CMOS two-port standard cell family utilizing a linear array layout topology with six to seven micron design rules and guardbanded n-channel devices has been developed. The process, structure, performance, and applications of this Expanded Linear Array (ELA) technology are described.

100000+ gates on a chip: mastering the minutia. II. Needed: a `miracle slice' for VLSI fabrication

For pt.I see ibid., vol.16, no.3, p.42 (1979). To achieve VLSI means micron and submicron design rules. It means large chips containing perhaps 100000 to 500000 gates, and it means perhaps processing power of a million instructions per second on a single chip. Clearly further ground must be broken in materials, patterning, processing, layout, design and testing, as well as architecture. Requirements for resistivities of more than 100 Ω-cm or minority carrier lifetimes of 500 μs may not be met with conventional silicon boule growth techniques. Silicon device yield and performance are limited by defects and impurity centers in the bulk, surface, and interface regions of the device structure. These can be intrinsic to the starting wafer or process induced. A final requirement for the miracle slice is that it be optically flat with a structurally perfect surface for whatever noncontact lithography technique is used, whether optical projection, projection step-and-repeat, E-beam, or X-ray.