Computer-aided design of an eight bit binary counter N-MOS chip for large scale integration (LSI)

Abstract

An integrated eight bit synchronous binary counter along with input/output circuits: gate protection, two phase clock, pad-out has been designed for MOS LSI. The counter has a master-slave flip-flop and a combinational logic to generate the next state, and outgoing carry outputs from this stage. The combination logic has been implemented using pass transistors and thus acts as a steering type logic. This type of logic is very fast, consumes lesser power and needs significantly less area for its implementation. Latest CAD techniques: interactive Graphics system of Applicon AGS/860 LSI Design Station, MOS circuit simulation program MSINC and Design Rule Check (DRC) program have been used for design and chip layout. The entire chip has been laid out in the area of 3 × 3 mm 2 including test devices and structures for testability analysis. The design is based on LOCOS N-MOS (E-D) technology and 8 micron design rules. The Electromask pattern generation (PG) tape has been prepared from Applicon for making chrome masks. A set of six masks have been used for the fabrication of device and die encapsulated in dual-in line package and tested for its performance. Counter works up to 5 MHz clock frequency as expected from design calculations. From 25 stage ring oscillator frequency measurement the gate delay comes out to be 6 nS. The counter design could easily be substituted as a sub-system/building block or cell in any MOS LSI system design where it makes a part of it.