Design of a High-Speed Binary Counter Using a Stacking Circuit

Abstract

A novel design of a binary counter is introduced in this paper. A 7:3 binary counter is designed using 5-bit and 2-bit stacking circuits, which is further merged and then converted into binary counts that bestow a binary stacking counter. This new design of binary stacking counter circuit does not have XOR gates or multiplexers in its critical path, which would turn out this circuit into a faster and efficient one. This innovative circuit is faster and has a better power efficiency which outperforms the conventional binary counter circuits. Hence, they find applications in deep learning and big data analysis.