Symmetric Stacking Based Fast Binary Counter Using Modified Gate Diffusion Input (M-GDI) Technique

Abstract

In this paper, modified-Gate Diffusion Input (M-GDI) based binary counter is designed using symmetric stacking method. The binary counter is designed using 3-bit stacker circuit that groups the one bit together and symmetric method is used to form 6-bit stack. The 6-bit stack is converted to binary count to produce required counters. The M-GDI is used to further reduce the transistor count than the CMOS logic transistor count. Mainly the basic gates are developed using the M-GDI technique and the basic gates are replaced in the 6:3 counters to further improve counter-performance. The proposed 6:3 binary counter has no Exclusive or gate (XOR) gates on the critical path, which leads to faster performance of the circuit. The proposed counter is faster, also consumes less power than the traditional. By using this proposed counter in Wallace multiplier, the delay and power for higher-order multipliers is reduced. This paper proposes a novel symmetric stacking based fast binary counters using the modified gate diffusion input (M-GDI) technique. This paper proposes a novel binary counter.