Microelectronics Center Of North Carolina Research Articles

Analysis of FPGA Architecture with Hybrid Logic Blocks Based on ULG and LUT

This paper analyzes the efficiency of different FPGA architectures consisting of Hybrid logic blocks (HLB) formed with Look-up Tables (LUTs) and Universal Logic Gates (ULGs). Pure LUT-based architectures induce area overhead and a longer delay. A ULG is designed to realize an efficient architecture compared to pure LUT-based architectures. Using this ULG and LUT in different proportions, HLBs are designed. The Field Programmable Gate Array (FPGA) architectures containing these proposed HLB structures are analyzed using various Microelectronics Centre of North Carolina (MCNC) benchmark circuits and compared with the performance of the existing designs. The result shows that the proposed architecture design can save a tremendous amount of time in overall flow and routing along with area improvements.

A Power Optimization Approach for Large-scale RM-TB Dual Logic Circuits Based on an Adaptive Multi-Task Intelligent Algorithm

Logic synthesis is a crucial step in integrated circuit design, and power optimization is an indispensable part of this process. However, power optimization for large-scale Mixed Polarity Reed-Muller (MPRM) logic circuits is an NP-hard problem. In this article, we divide Boolean circuits into small-scale circuits based on the idea of divide and conquer using the proposed Dynamic Adaptive Grouping Strategy (DAGS) and the proposed circuit decomposition model (CDM). Each small-scale Boolean circuit is transformed into an MPRM logic circuit by a polarity transformation algorithm. Based on the gate-level integration, we integrate small-scale circuits into an MPRM and Boolean Dual Logic (RBDL) circuit. Furthermore, the power optimization problem of RBDL circuits is a multi-task, multi-extremal, high-dimensional combinatorial optimization problem, for which we propose an Adaptive Multi-task Intelligent Algorithm (AMIA), which includes global task optimization, population reproduction, valuable knowledge transfer (VKT), and local exploration to search for the lowest power for RBDL circuits. Moreover, based on the proposed Fast Power Decomposition Algorithm (FPDA), we proposed a Power Optimization Approach (POA) for an RBDL circuit with the lowest power using the AMIA. Experimental results based on Microelectronics Center of North Carolina (MCNC) Benchmark test circuits demonstrate the effectiveness and superiority of the POA compared to state-of-the-art POAes.

An Optimal Partitioning and Floor Planning for VLSI Circuit Design Based on a Hybrid Bio-Inspired Whale Optimization and Adaptive Bird Swarm Optimization (WO-ABSO) Algorithm

Partitioning and Floor Planning are two of the design processes in the VLSI design and are used to reduce the size of the circuit. Area and interconnect length reduction are the key goals for physical design automation of very large-scale integration chips in VLSI physical design optimization. The aim of decreasing the area and interconnect length is to decrease the integrated chip’s size. To achieve the above objective and to achieve the aforementioned goal, an ideal solution for physical design components, like partitioning, floor planning must be found. The existing methods did not provide the sufficient results for Partition and Floor Plan. Therefore, in this paper, an Optimal Partitioning and Floor Planning for the VLSI Circuit Design based on Hybrid Bio-inspired Whale Optimization and Adaptive Bird Swarm Optimization (WO-ABSO) Algorithm are proposed. The goal of hybrid WO-ABSO algorithm for decreasing the delay for partitioning, decreasing the area for floor planning, decreasing the delay, wire length in floor planning has indefinite influence on other criteria, such as power and speed. Here, the circuit partitioning problem is optimized using whale optimization algorithm and the floor planning problem is optimized under ABSO algorithm. The benchmark tests included test cases from Microelectronics Center of North Carolina (MCNC) benchmark circuits. The proposed hybrid WO-ABSO algorithm attains lower area, lower delay, and lower power usage compared with the existing methods.

Shared reduced ordered binary decision diagram‐based thermal‐aware network synthesis

SummaryIn this work, a multi‐objective algorithm based on nondominated sorting genetic algorithm‐II (NSGA‐II) for thermal‐aware realization of a combinational logic network has been implemented. Input variable ordering of shared reduced ordered binary decision diagram (SROBDD) is done using NSGA‐II such that resulting combinational circuit generates low hotspots by suitable power density distribution. Simultaneous co‐optimization among area, power, and temperature is important in the higher levels of electronic circuit design to reduce the cooling cost. Using a multi‐objective algorithm (NSGA‐II), an effort is made to decrease the temperature by co‐optimization between the power density, area, and power simultaneously. Microelectronics Center of North Carolina (MCNC) benchmark circuits are tested using the proposed approach and an improvement of 13.65% in the silicon area and up to 10% in power dissipation, and 2.72% peak temperature reduction is reported in comparison to existing literature. HotSpot tool and Cadence Innovus are used to determine the peak temperature, actual silicon chip area, and power dissipation of algorithmic optimized solutions.

A Heuristic Boolean NPN Equivalent Matching Verification Method Based on Shannon Decomposition

In this paper, we describe a new verification method to accelerate the input negation and/or input permutation and/or output negation (NPN) Boolean matching for a single-output completely specified Boolean function. Through research on the Boolean Shannon decomposition binary tree, we prove that the signature vectors of the left child node and right child node are complementary relative to the signature vector of the parent node. We introduce an independent variable check to speed up the detection of candidate transformation. The proposed approach utilises this complementarity, a symmetry check, an independent variable check and a phase collision check, which can quickly verify whether the candidate transformation obtained in the detection of the candidate transformation of the Boolean matching process is accurate. We perform experiments on two types of Boolean function sets. One type consists of Boolean functions from randomly generated circuits. The other is exported from the Microelectronics Center of North Carolina (MCNC) benchmark. The experimental results show that the average runtime of our algorithm is 68.8% faster than those in Zhang et al. (2019) on two randomly generated circuits and 51% faster than those in Zhang et al. (2019) when tested on the MCNC benchmark circuit set. Therefore, the experimental results demonstrate the effectiveness of the proposed method.

Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms

This paper introduces hybrid iterative algorithms that combine Particle Swarm Optimization (PSO) and Simulated Annealing (SA) algorithms for Field Programmable Gate Array (FPGA) placement by considering adaptive inertia weight and local minima avoidance. The algorithms target to optimize the wire-length of the nets, run time and critical path delay in the placement of logic blocks. Using the adaptive inertia weight parameter and local minima avoidance, the hybrid PSO-SA algorithm is modified to Time-varying PSO-SA (TPSO-SA) and Modified PSO-SA (MPSO-SA) algorithm, respectively. These different hybrid PSO-SA algorithms are checked for efficiency by comparing with the Versatile Place and Route (VPR) algorithm of the Verilog to Routing (VTR) tool using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The hybrid PSO-SA algorithms give 5–37% better results for wire-length cost and 20–58% reduction in runtime compared to the VPR placement algorithm on different benchmark circuits. Critical path delay is also taken into consideration.

DOTFloor–A Diffusion Oriented Time-Improved Floorplanner for Macrocells

This work presents a unique time-efficient and reliable floorplan algorithm DOTFloor (Diffusion Oriented Time-improved Floorplanner), built around a SA (Simulated Annealing) engine and targeted to optimize the peak on-chip temperature along with the traditional design metrics like chip area and wire length. This paper also proposes a novel heat-diffusion based stochastic thermal model called the FATT (Fast Assumption Technique for Temperature) which provides a fast assumption of the degree of hotness during the optimization process. The incorporation of FATT in DOTFloor results in a significant improvement in the run time of the optimization process. Upon experimentation on MCNC (Microelectronics Center of North Carolina) benchmark circuits with the proposed floorplanner, a good optimization in area, wire length metric and peak on-chip temperature with a significant reduction in execution time have been achieved over the existing floorplanning tool, the HotFloorplan.

Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm

Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.

3D VLSI Non-Slicing Floor Planning using Modified Corner List Representation

Background: Floor planning is important step in physical design automation of VLSI circuits, because it gives an early feedback on the architectural design. It is the process of finding the position of the module such that no two modules overlap with each other. Methods: In order to have an efficient floor plan, the total area occupied by the modules should be minimum. So, non-slicing floor plan is used to find an optimal floor plan layout. To represent non-slicing floor plan, a number of representations are proposed. Findings: To encompass billions of transistors in an Integrated Circuit (IC), 3Dimensional (3D) IC is preferred instead of 2D. In this paper, a novel 3Dimensional (3D) non-slicing floor planning representation called Modified Corner List (MCL) algorithm is proposed and properties of MCL algorithm is derived. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits and simulation results shows that it is very effective for 3D floor plan representation. Improvements: The proposed algorithm works well for small number of modules. As the number of module increases, computational time taken by the algorithm also increases. The above problem can be solved by applying heuristic algorithm in association with MCL strategy to find near optimal placement in reduced run time.

Designing Trusted Embedded Systems from Finite State Machines

Sequential components are crucial for a real-time embedded system as they control the system based on the system's current state and real life input. In this article, we explore the security and trust issues of sequential system design from the perspective of a finite state machine (FSM), which is the most popular model used to describe sequential systems. Specifically, we find that the traditional FSM synthesis procedure will introduce security risks and cannot guarantee trustworthiness in the implemented circuits. Indeed, we show that not only do there exist simple and effective ways to attack a sequential system, it is also possible to insert a hardware Trojan Horse into the design without introducing any significant design overhead. We then formally define the notion of trust in FSM and propose a novel approach to designing trusted circuits from the FSM specification. We demonstrate both our findings on the security threats and the effectiveness of our proposed method on Microelectronics Center of North Carolina (MCNC) sequential circuit benchmarks.

Variable-Order Ant System for VLSI multiobjective floorplanning

Floorplanning is crucial in VLSI chip design as it determines the time-to-market and the quality of the product. In this work, Variable-Order Ant System (VOAS) is developed and combined with a floorplan model namely Corner List (CL) to optimize the area and wirelength. CL is used to represent the floorplan layout. Although CL has proven to have the same search space and time complexity as Corner Sequence (CS), comparatively, CL has more corners to be selected. This compensates the sequence weakness, where modules can be placed freely onto the corners, which are not bounded by the floorplan contour. Two groups of ants, namely VOAS and reconnaissance ants, which will collaborate with each other to determine the local information, are introduced. Through this cooperation, VOAS ant can ascertain its local information greedily, based on the local search space information carried out by reconnaissance ants. Subsequently, VOAS ant proposes a new variable-order property to prioritize the global and local explorations. The variable-order property enables the ants in VOAS to weigh a better choice of modules for the floorplanning, based on the local and global information. The update rules of VOAS are modified in order to handle two-dimensional problem, such as VLSI floorplanning. VOAS shows improved results in terms of purely area optimization as well as composite function of area and wirelength, as compared to other state-of-the-art and recent floorplanning/placement algorithms based on Microelectronics Centre of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC) benchmarks.

Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

Abstract —Placement is important in VLSI physical design as it determines the time-to-market and chip’s reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS) is proposed. Though CIS’s search complexity is smaller than the state-of-the-art representation Corner Sequence (CS), CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC) hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS. Index Terms—Design, system, aided, floorplanning, VLSI, representation, circuits, algorithm, scale, optimization. I. I NTRODUCTION In the modern IC design flow, a placement of an IC is a schematic representation of placement of its major functional blocks. As the Very Large Scale Integration (VLSI) chip keeps shrinking in size, many factors such as the total area [1-2], wirelength [3-5], power consumption [6-7] and congestion reduction [8-9] will affect the reliability and efficiency of the chip. Hence, to cope up with these issues, efficient placement plays a very crucial role as far as the quality of the VLSI design is concerned. The VLSI placement design problem is well-known as the NP-hard problem and hence it is difficult to find exactly optimal solution in practical applications [10-11]. In order to solve this combinatorial optimization problem, placement layout is tackled mathematically in order to be optimized using the tools such as mathematical optimization or artificial intelligence (AI) technique. Many approaches [1], have been proposed in the literature with different modeling representations [12-15] and optimization methods [2], [5], [16-17] to enhance the quality of the placement design. To facilitate a good placement, it is necessary to develop an effective model for blocks placement to reduce the dead space area as well as minimizing the placement runtime. II. P

Hierarchical congregated ant system for bottom-up VLSI placements

A new perturbation method, called Hierarchical-Congregated Ant System (H-CAS) has been proposed to perform the variable-order bottom-up placement for VLSI. H-CAS exploits the concept of ant colonies, where each ant will generate the perturbation based on differences in dimensions of the VLSI modules in hard modules floorplanning and differences in area of the VLSI modules in soft modules floorplanning. In this paper, it is mathematically proved that the area-based two-dimensional cost function for hard modules floorplanning problem can be reduced to the difference-based one dimensional cost function which avoids local optima problems. Lack of global view is a major drawback in the conventional bottom-up hierarchy, and hence, ants in the H-CAS are made to introduce global information at every level of bottom-up hierarchy. A new relative whitespace formula for bottom-up hierarchy is derived mathematically and the H-CAS embeds it in its unique update formula. The ants in H-CAS are able to communicate among themselves and update the pheromone trails when they reach the destination. Then, the ants will congregate, share their experiences and construct a new pheromone trails that belong to this newly constructed group. The congregation of at least two ants and/or ant consortiums would lead to reduction in subsequent search space and complexity. H-CAS gives the best-so-far near optimal solutions and yields low standard deviations of areas involving 9–600 blocks based on Microelectronics Center of North Carolina (MCNC) and Giga scale Systems Research Center (GSRC) benchmarks. The results obtained establish that H-CAS is a high performance placer in respect of scaling, convergence, precision, stability, and reliability. The above claims are based on the comparisons with the other floorplanning algorithms as depicted graphically.

A multiobjective optimization tool for Very Large Scale Integrated nonslicing floorplanning

ABSTRACTFloorplanning is a vital phase in the design process of Very Large Scale Integrated (VLSI) circuit physical design process. The main objective of floorplanning is to minimize the area and wire length with the fixed‐outline constraints. Most of the tools developed so for are using weighted some approach. Hence, these tools suffer from weights assignment and undesirable bias toward particular objective. A tailor‐made multiobjective optimization tool could overcome this issue.In this article, we propose a new multiobjective optimization technique named self adaptive B*tree coded Archived Multiobjective Simulated Annealing Algorithm (AMOSA) and implemented to solve the VLSI nonslicing floorplanning problem. The proposed model provides choices from among different trade‐off solutions. The self adaptive B*tree coded AMOSA combines the novel cooling schedule, B*tree encoding, improved neighborhood search procedure, self adaptive local search, and the AMOSA. In B*tree coded AMOSA, the solution is represented using a B*tree. This representation causes a reduction in time and space complexity of AMOSA. The B*tree coded AMOSA is further improved with a novel cooling schedule, a self adaptive local search mechanism, and an improved neighborhood search procedure, resulting in further reduction of computational time and improvement in exploration capability. The FastSA, B*tree coded AMOSA, and the self adaptive B*tree coded AMOSA are tested with Microelectronics Center of North Carolina (MCNC) benchmarks. The results are compared and validated. The proposed method shows 59.8% improvement in the computational time for ami49 without changing the system quality. Copyright © 2012 John Wiley & Sons, Ltd.

Customized simulated annealing based decision algorithms for combinatorial optimization in VLSI floorplanning problem

Modern very large scale integration technology is based on fixed-outline floorplan constraints, mostly with an objective of minimizing area and wirelength between the modules. The aim of this work is to minimize the unused area, that is, dead space in the floorplan, in addition to these objectives. In this work, a Simulated Annealing Algorithm (SAA) based heuristic, namely Simulated Spheroidizing Annealing Algorithm (SSAA) has been developed and improvements in the proposed heuristic algorithm is also suggested to improve its performance. Exploration capability of the proposed algorithm is due to the mechanism of reducing the uphill moves made during the initial stage of the algorithm, extended search at each temperature and the improved neighborhood search procedure. The proposed algorithm has been tested using two kinds of benchmarks: Microelectronics Center of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC). The performance of the proposed algorithm is compared with that of other stochastic algorithms reported in the literature and is found to be efficient in producing floorplans with very minimal dead space. The proposed SSAA algorithm is also found more efficient for problems of larger sizes.

ANT COLONY OPTIMIZATION FOR VLSI FLOORPLANNING WITH CLUSTERING CONSTRAINTS

In this study the very large scale integration (VLSI) floorplanning problem with clustering constraints and the layout area as the minimization criterion is considered. An algorithm, which is based on the primary principles of ant colony optimization (ACO), to solve this problem is presented. This ACO-based algorithm employs two different types of pheromone trails as the communication media among artificial ants to effectively guide them to cooperatively construct a high quality floorplan. On the basis of the characteristics of ACO, moreover, an encoding scheme, which is referred to as dynamic junction list (DJL), is proposed to represent the geometric relationships between circuit modules for a floorplan. Experimental results using the Microelectronics Center of North Carolina (MCNC) benchmarks demonstrate the effectiveness of the proposed algorithm.

Temperature-aware floorplanning via geometric programming

With microprocessor power densities escalating rapidly when technology scales below nanometer regime, there is an exigent need for developing innovative cooling systems for electronic product design. The high temperature of chips greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling systems significantly more expensive. The maximum temperature of a block in a chip depends not only on its own power density, but also on the chip area in each blocks. In this paper, we employ geometric programming (GP) for the optimization problem of temperature reduction and chip area floorplanning. We notice that the formulated model is a nonlinear convex problem; consequently, its solution can be solved GP method. Based upon an incremental floorplanning problem together with the GP model, the temperature-aware floorplanning scheme significantly reduces peak module temperature with minimal chip area impact. For Microelectronics Center of North Carolina (MCNC) ami33 under a testing environment temperature of 0 ∘C, compared with the maximum temperature of the original module, the maximum temperature of the optimized one could be reduced from 90 ∘C to 10 ∘C, where the minimized chip area is about 700 mm 2. For the case of MCNC ami49, the maximum temperature reduction is 60 ∘C (i.e., its reduction is from 65 ∘C to 5 ∘C) with a minimal chip area of 2500 mm 2. We have numerically found a floorplan which can reduce the maximum temperature of the chip and minimize the chip area while maintaining comparable performance simultaneously.

A three-step decomposition method for the evolutionary design of sequential logic circuits

Evolvable hardware (EHW) refers to an automatic circuit design approach, which employs evolutionary algorithms (EAs) to generate the configurations of the programmable devices. The scalability is one of the main obstacles preventing EHW from being applied to real-world applications. Several techniques have been proposed to overcome the scalability problem. One of them is to decompose the whole circuit into several small evolvable sub-circuits. However, current techniques for scalability are mainly used to evolve combinational logic circuits. In this paper, in order to decompose a sequential logic circuit, the state decomposition, output decomposition and input decomposition are united as a three-step decomposition method (3SD). A novel extrinsic EHW system, namely 3SD---ES, which combines the 3SD method with the (μ, ?) ES (evolution strategy), is proposed, and is used for the evolutionary designing of larger sequential logic circuits. The proposed extrinsic EHW system is tested extensively on sequential logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The results demonstrate that 3SD---ES has much better performance in terms of scalability. It enables the evolutionary designing of larger sequential circuits than have ever been evolved before.

ANT COLONY OPTIMIZATION FOR VLSI FLOORPLANNING WITH CLUSTERING CONSTRAINTS

ABSTRACT In this study the very large scale integration (VLSI) floorplanning problem with clustering constraints and the layout area as the minimization criterion is considered. An algorithm, which is based on the primary principles of ant colony optimization (ACO), to solve this problem is presented. This ACO-based algorithm employs two different types of pheromone trails as the communication media among artificial ants to effectively guide them to cooperatively construct a high quality floorplan. On the basis of the characteristics of ACO, moreover, an encoding scheme, which is referred to as dynamic junction list (DJL), is proposed to represent the geometric relationships between circuit modules for a floorplan. Experimental results using the Microelectronics Center of North Carolina (MCNC) benchmarks demonstrate the effectiveness of the proposed algorithm.

A FAST AND EFFECTIVE TIMING-DRIVEN PLACEMENT TOOL FOR FPGAs

In this paper, we present TQPF, a Timing-Driven Quadratic-based Placement Tool for FPGAs. Quadratic placement algorithms try to minimize total squared wire length by solving linear equations. The resulting placement tends to locate all cells near the center of the chip with a large amount of overlap. Also, since squared wire length is only an indirect measure of linear wire length, the resulting total wire length may not be minimized. We propose methods to alleviate the above two problems that give high-quality results while minimizing the total run time. We incorporate multiple iterations of equation-solving process together with a technique for pulling nodes out of the dense area while minimizing linear wire length. Experimental results using 20 Microelectronics Center of North Carolina (MCNC) benchmark circuits show that, on average, TQPF is approximately three times faster than the well-known Versatile Placement and Routing tool for FPGAs (VPR). The estimated total wire length, on average, is only 1.4% longer, and the critical path delay is 4.9% lower.