Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

Abstract

Abstract —Placement is important in VLSI physical design as it determines the time-to-market and chip’s reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS) is proposed. Though CIS’s search complexity is smaller than the state-of-the-art representation Corner Sequence (CS), CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC) hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS. Index Terms—Design, system, aided, floorplanning, VLSI, representation, circuits, algorithm, scale, optimization. I. I NTRODUCTION In the modern IC design flow, a placement of an IC is a schematic representation of placement of its major functional blocks. As the Very Large Scale Integration (VLSI) chip keeps shrinking in size, many factors such as the total area [1-2], wirelength [3-5], power consumption [6-7] and congestion reduction [8-9] will affect the reliability and efficiency of the chip. Hence, to cope up with these issues, efficient placement plays a very crucial role as far as the quality of the VLSI design is concerned. The VLSI placement design problem is well-known as the NP-hard problem and hence it is difficult to find exactly optimal solution in practical applications [10-11]. In order to solve this combinatorial optimization problem, placement layout is tackled mathematically in order to be optimized using the tools such as mathematical optimization or artificial intelligence (AI) technique. Many approaches [1], have been proposed in the literature with different modeling representations [12-15] and optimization methods [2], [5], [16-17] to enhance the quality of the placement design. To facilitate a good placement, it is necessary to develop an effective model for blocks placement to reduce the dead space area as well as minimizing the placement runtime. II. P