MHz Operation Research Articles

Analysis and Design Capacitive Power Transfer (CPT) System for Low Application Using Class-E LCCL Inverter by Investigate Distance between Plates Capacitive.

This study presents the analysis and design of a Capacitive Power Transfer (CPT) system for low power application using a Class-E LCCL inverter based on varying the distance between capacitance plates. The Class-E LCCL inverter can produce a high-frequency alternate current and reduce the size of the capacitance plate to minimise power losses during energy transfer besides yielding low switching losses. In specific, the performance of the LCCL CPT system at 1 MHz operating frequency and 24 V DC supply voltage was analysed via simulation and experimental works. Finally, a prototype of the CPT system was successfully designed, producing 10 W output power through a capacitive plate size of 0.0327 m2 and a 0.1 cm air gap at 96.68% efficiency. Based on the performance of the LCCL CPT System design, an efficiency analysis of the LCCL CPT System was performed; the capacitance plate distance was varied from 1 cm to 20 cm and produced a change in total impedance calculation from 57.69+j198.42 Ohm to −2.05j Ohm. Meanwhile, efficiency decreased from 96.68% to 1.25% but power was still transmitted in that range. These findings could be beneficial for hazardous electrical environments, portable applications, consumer electronics, and medical implants.

Effect of low frequency power on the electron energy distribution function in argon inductively coupled plasmas

In plasma processing and application, the electron energy distribution function (EEDF) is of fundamental interest because the ion and radical densities related to physical and chemical reactions on the substrate are predominantly governed by the EEDF or electron temperature. In this paper, the effect of low frequency power on the EEDF is investigated when 2 MHz power is added to the plasma originally driven at 13.56 MHz. In a 13.56 MHz operation, the EEDF shows a Maxwellian-like distribution, and as the RF power increases, the electron density increases and the electron temperature decreases. However, when a small amount of 2 MHz power is applied to the 13.56 MHz discharge, the electron density slightly increases and the electron temperature significantly increases. In dual-frequency operation, EEDFs have a low slope of low-energy region and evolve into a Druyvesteyn-like distribution. It turns out that the dual-frequency operation can significantly change the electron temperature. This is consistent with the results calculated using the analytical electron heating model, and the relevant heating mechanism is also presented.

Coil Inductance Design for Low Power Hybrid Wireless Power Transfer

This paper presents a coil inductance design for low power hybrid wireless power transfer (WPT). The proposed coil inductance design of transmitter and receiver circuits of 7.1 μH are designed using handmade copper wire structure. Several coils with the variations of wire diameters, coil loop radius, and numbers of loops are proposed to find optimum structure in the low power hybrid WPT. The optimum coil structure is obtained at wire diameter of 0.5 mm, 2.25-inch coil loop radius and 1 MHz operation frequency. The measured transceiver coil design has exhibited peak power transfer efficiency (PTE) of 33.1% at 1 cm distance between Tx and Rx. Therefore, the proposed coil design is applicable to low power hybrid wireless power transfer circuits.

A 4-tap global shutter pixel with enhanced IR sensitivity for VGA time-of-flight CMOS image sensors

An indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7 μm global shutter pixel in back-side illumination process. 15000 e- of high full-well capacity (FWC) per a tap of 3.5 μm pitch and 3.6 e- of read-noise has been realized by employing true correlated double sampling (CDS) structure with storage gates (SGs). Noble characteristics such as 86 % of demodulation contrast (DC) at 100MHz operation, 37 % of higher quantum efficiency (QE) and lower parasitic light sensitivity (PLS) at 940 nm have been achieved. As a result, the proposed ToF sensor shows depth noise less than 0.3 % with 940 nm illuminator in even long distance.

VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network

Hardware accelerators for convolution neural networks (CNNs) enable real-time applications of artificial intelligence technology. However, most of the existing designs suffer from low hardware utilization or high area cost due to complex data flow. This paper proposes a hardware efficient vectorwise CNN accelerator that adopts a 3 × 3 filter optimized systolic array using 1-D broadcast data flow to generate partial sum. This enables easy reconfiguration for different kinds of kernels with interleaved input or elementwise input data flow. This simple and regular data flow results in low area cost while attains high hardware utilization. The presented design achieves 99%, 97%, 93.7%, and 94% hardware utilization for VGG-16, ResNet-34, GoogLeNet, and Mobilenet, respectively. Hardware implementation with TSMC 40nm technology takes 266.9K NAND gate count and 191KB SRAM to support 168GOPS throughput while consumes only 154.98mW when running at 500MHz operating frequency, which has superior area and power efficiency than other designs.

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology

A 0.5V ultra-low voltage Arm Cortex-M4F MCU in a 22nm FDSOI technology with 512kB SRAM and 140MHz operating frequency with 11.5μW/MHz is presented. An all-digital closed-loop continuous adaptive body biasing with individual P and N compensation and low ripple less than 30mV enables target performance from -40°C to 125°C and over full process corner range. The MCU has been implemented using an adaptive body bias aware implementation flow, which considers the corner tightening during implementation and sign-off for improved power, performance and area.

A Compact Adder and Reprogrammable Logic Gate Using Micro-Electromechanical Resonators With Partial Electrodes

In this brief, the design principles and experimental demonstration of a compact full adder along with a reprogrammable 4-input logic gate are presented. The proposed solution for implementation of digital circuits is based on a clamped–clamped micro-beam resonator with multiple split electrodes, in which the logic inputs tune the resonance frequency of the beam. This technique enables re-programmability during operation, and reduces the complexity of the digital logic design significantly; as an example, for a 64-bit adder, only 128 micro-resonators are required, compared to more than 1500 transistors for standard complementary metal–oxide–semiconductor (CMOS) architectures. We also show that an optimized simulated micro-resonator-based full adder is 45 times smaller than a CMOS mirror adder in 65-nm technology. While the energy consumption of this early generation of micro-resonator logic gates is higher than the CMOS solutions, we show that by careful device optimization and shrinking of the dimensions, femtojoules energy consumption and MHz operation, required by Internet of Things applications, are attainable.

A Granular Resampling Method and Adaptive Speculative Mechanism-Based Energy-Efficient Architecture for Multiclass Heartbeat Classification

This brief presents an energy-efficient design with cascaded structure aiming at multiclass heartbeat classification. support vector machine-based granular resampling method is put forward to obtain a hybrid classifier which includes a low-complexity model (LCM) to identify most easy-to-learn heartbeats and a high-accuracy classifier to discriminate the remained. The hybrid classifier combined with one-versus-all strategy is employed to achieve a multiclass classification model. An adaptive speculative mechanism based on the occurrence regularity of electrocardiogram abnormities is proposed to lower the complexity and computation burden of the multiclass classification model. The corresponding energy-efficient hardware architecture is designed and its architecture optimizations include memory segmentation to reduce energy consumption and time domain reuse to save resources. Implemented in 40-nm CMOS process, the design occupies 0.135 mm2 area. It consumes 2.60–48.99 nJ/classification under 1-V voltage supply and 1 MHz operating frequency. Results show that the design provides an average prediction speedup by 60.66% and a significant energy dissipation reduction by 55.26% per beat compared with a high-accuracy model without LCMs.

Development of memory controller for today’s Elbrus microprocessors

The introduction of a new generation of microprocessors that belong to the Elbrus family and involve the introduction of a network-on-chip, requires the development of efficient means of access to DDR random access memory channels for network nodes. The paper includes a solution to this issue related to the interaction between DDR4 RAM and Elbrus-16СВ, 16-core microprocessor, which demands higher standards of an available capacity and peak bandwidth of memory channels. When designing Elbrus-16CB microprocessor, higher energy efficiency and reliability are also between main objectives. When performing the tasks set, an important component was adaptation of the memory controller, successfully applied in the microprocessors produced by MCST JSC, to DDR4 3DS standard compliance, taken as a basis for the use in a number of recent developments. It provides a four-time higher available RAM capacity without a directly proportional growth of energy consumption. The paper includes a structure of the memory controller and made decisions. These make it possible to increase the target frequency in operations of the device by 30% up to 800 MHz and increase operation reliability of the memory channel.

Towards a Miniaturized 3D Receiver WPT System for Capsule Endoscopy.

The optimization, manufacturing, and performance characterization of a miniaturized 3D receiver (RX)-based wireless power transfer (WPT) system fed by a multi-transmitter (multi-TX) array is presented in this study for applications in capsule endoscopy (CE). The 200 mm outer diameter, 35 μm thick printed spiral TX coils of 2.8 g weight, is manufactured on a flexible substrate to enable bendability and portability of the transmitters by the patients. The 8.9 mm diameter—4.8 mm long, miniaturized 3D RX—includes a 4 mm diameter ferrite road to increase power transfer efficiency (PTE) and is dimensionally compatible for insertion into current endoscopic capsules. The multi-TX is activated using a custom-made high-efficiency dual class-E power amplifier operated in subnominal condition. A resulting link and system PTE of 1% and 0.7%, respectively, inside a phantom tissue is demonstrated for the proposed 3D WPT system. The specific absorption rate (SAR) is simulated using the HFSSTM software (15.0) at 0.66 W/kg at 1 MHz operation frequency, which is below the IEEE guidelines for tissue safety. The maximum variation in temperature was also measured as 1.9 °C for the typical duration of the capsule’s travel in the gastrointestinal tract to demonstrate the patients’ tissues safety.

A scheme of bipartite microwave polarization entanglement based on Josephson mixer

The basic principles for preparation and detection of continuous variable polarization entanglement in quantum optics, as well as the generalized criterion of bipartite polarization entanglement, are briefly introduced. Based on theories and experiments in quantum optics, a scheme of bipartite quantum microwave polarization entanglement is proposed and simulated. Inseparability of Stokes vector as I(Ŝ1,Ŝ2) and I(Ŝ2,Ŝ3) are obtained in order to witness the polarization entanglement in 100 MHz operation bandwidth of Josephson mixer. Furthermore, relations between inseparability I and squeezing parameter r as well as amplitude ratio Q are discussed respectively. The results show that I(Ŝ1,Ŝ2) is sensitive of the variance of Q, while I(Ŝ2,Ŝ3) seems to be sensitive of the variance of r. Meanwhile, I(Ŝ1,Ŝ2) remains above 1 in the paper, while I(Ŝ2,Ŝ3) is on the contrary well below 1. It can be concluded that Ŝ2 and Ŝ3 of Stokes vectors are inseparable, which means that output signals Êa and Êb of the scheme exhibit bipartite entanglement in polarization. The best entanglement appears at 70 MHz or so with the minimum I(Ŝ2,Ŝ3) value of 0.25. Apart from these, precision of witness for polarization entanglement and quadrature entanglement is compared. Polarization entanglement appears to be easier and more precise to witness according to our research.

Low-Complexity Architecture for Cyber-Physical Systems Model Identification

We propose a low complexity architecture for cyber-physical system (CPS) model identification based on multiple-model adaptive estimation (MMAE) algorithms. The complexity reduction is achieved by reducing the number of multiplications in the filter banks of the MMAE algorithm present in the cyber component of the CPS. The architecture has been implemented using FPGA for 16, 32, 64 filter banks as part of position and velocity estimations of autonomous auto-mobile application. It has been found up to 78% reduction in multiplications is possible, which translates to the reduction of 39% lookup tables, 13% FFs, 27% DSPs, and 43% power reduction when compared with the conventional architecture (without multiplications reduction) at 100MHz operating frequency. Furthermore, the proposed architecture is able to identify accurate model of auto-mobile application just within 510 ns, in the presence of external disturbances and abrupt changes.

CMUT-based biosensor with convolutional neural network signal processing

The improvement of the micromachined ultrasound transducer based (CMUT) biosensor fabrication technology and signal processing, which led to higher signal to noise ratio is reported. The biosensor contains interdigitally arranged CMUT structure with gold-coated analytical area. It is assembled with the plexiglass microchannels. CMUTs were fabricated with the wafer bonding technology for 5 MHz operation in immersion. For signal processing the convolutional neural network (CNN) was developed and trained to classify the sensor data to different propagation delay values. For training of the network 750 thousand signals representing different properties of the bioanalyte and different noise conditions was simulated by the finite time difference domain (FDTD) model. The capability of the CNN algorithm to classify the propagation delay data was compared with the adaptive passband filter signal processing algorithm used in our previous version of the senor. Both sensing channels were run simultaneously with the reference liquids in the microchannel: deionized water switching to 0.9% saline. It was found that CNN channel is capable to improve the signal to noise ratio for this experiment to 75 dB, when the same property for the passband filter channel was only 60 dB. This led to the generalization about the advantage of CNN channel to provide 15 dB less of instrumental noise. Finally, the real-time detection ability of the bovine serum albumin (BSA) deposition on the analytical area of improved sensor was demonstrated.

WHT and Matrix Decomposition-Based Approximated IDCT Architecture for HEVC

This brief proposes a new model of inverse discrete cosine transform (IDCT) kernel for high efficiency video coding (HEVC). The kernel supports IDCT of order 4, 8, 16, and 32. The proposed architecture uses the Chen’s algorithm as well as Walsh–Hadamard transform-based matrix decomposition method for complexity reduction. Additionally, an approximation scheme is proposed to replace all the coefficients by dyadic fractions on the basis of orthogonality and normality errors. As a consequence, the entire transform can be realized by using add and shift operations and hence, rotation unit is inessential. This reduces hardware cost significantly and the speed of the architecture also gets enhanced. The proposed approximated model complies with the requirements of HEVC and during video coding, less than 0.5 dB PSNR variation is observed as compared to that of the HEVC reference software. The proposed integer IDCT architecture is implemented on CMOS 90-nm ASIC platform. It is observed that it requires 36.6K logic gates at 200 MHz operating frequency.

Design of a Microwave Global Endometrial Ablation Device

Endometrial ablation is a minimally invasive treatment employed for thermal coagulation of the endometrial lining of the uterus for treatment of menstrual heavy bleeding. Here, we present an applicator employing a microwave loop antenna for global endometrial ablation enabling conformal ablation of uterine cavities of varying size in the range 4–6.5 cm in length and 2.5–4.5 cm in width, with a single positioning of the device. For treating large cavities, conformal microwave radiation is achieved by coupling the loop antenna with a passive element. A 3-D-coupled finite element method electromagnetic and heat transfer simulator was employed to optimize the antenna geometry with the goal of maximizing return loss at the 915 MHz operating frequency, and achieving adequate ablation depths for a range of uterine cavity sizes. Proof-of-concept devices were fabricated and experimentally evaluated in ex vivo tissue. The simulated and measured return loss of the optimized design was 20 dB at 915 MHz. Experiments in ex vivo tissue demonstrated the ability of the presented device to achieve mean ablation depths of 7.3 mm. We demonstrated a technique for creating planar ablation patterns suitable for global endometrial ablation of different uterine cavity sizes by employing a loop antenna with a passive element. Our design provides a planar ablation pattern by using a loop antenna with a passive element that will allow for ablation applications not realizable with conventional coaxial monopole, dipole, and slot antennas.

An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI

A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used along with poly and back-gate biasing techniques to achieve an adequate balance between the drive strength of the pull-up and pull-down networks. Measurements showed that the lowest input voltage levels, which could be upconverted by the 10 chip samples, varied from 39 mV to 52 mV. Half of the samples could upconvert from 39 mV to 1 V. The simulated energy consumption of the level shifter was 5.2 fJ for an up-conversion from 0.2 V to 1 V and 1 MHz operating frequency.

Cascaded Boost‐Class‐E for rotary capacitive power transfer system

This paper presents a capacitive power transfer (CPT) system design for low-power rotary applications. The aim of a rotary CPT system is to be free of power cables so it can achieve 360 degrees of free rotation, while remaining simple and easy to clean. In this work, a class-E high-frequency inverter with second-order LC compensation is proposed to drive the rotary CPT system. An LC compensation circuit is applied on both stationary and rotating sides in order to maximise the power transfer by increasing the voltage across the coupling plates. By implementing the proposed technique, the Class-E LCCL rotary CPT system that is efficient and less sensitive to load variations can be achieved. A Boost converter is also proposed here to provide input impedance matching and tune the input power of the Class-E LCCL rotary CPT system. A 10 W multiple plate rotary CPT prototype based on cascaded Boost- Class E LCCL is designed and implemented to demonstrate efficient wireless power transfer (WPT) across the rotating load. The results reveal >76% power transfer efficiency is successfully achieved at 1 MHz operating frequency and with 7.67 W output power.

A 2–10 MHz GaN HEMTs Half-Bridge Driver With Bandgap Reference Comparator Clamping and Dual Level Shifters for Automotive Applications

Gallium nitride (GaN) high electron mobility transistors (HEMTs) are promising power devices due to their excellent characteristics. However, GaN HEMTs have vulnerable gates that are susceptible to noise and voltage spikes, limiting their implementation in power converters. This paper presents a GaN HEMTs half-bridge driver with bandgap reference comparator clamping (BGRCC) and dual level shifters (DLS) for high switching frequency automotive applications. The BGRCC scheme can adaptively clamp the bootstrap rail voltage at an appropriate level with acceptable voltage ripples, which guarantees the safety of high-side GaN HEMT. Meanwhile, DLS scheme is applied in both the high- and low-side driving path to effectively drive the GaN HEMTs with low propagation delay and high dv / dt immunity. The proposed driver is fabricated in 0.18 μm high voltage bipolar-complementary metaloxide semiconductor (CMOS)-double-diffused metaloxide semiconductor (DMOS) process and can support 2–10 MHz operating. The functionality and performance are verified by experimental results. A buck converter utilizing this driver with GaN HEMTs can achieve maximum efficiency of 91.58% with quite electromagnetic interference behavior in the 16.5-W output power rating when operating at 2 MHz, which is superior to conventional silicon-based power converters and suitable for automotive applications.

Hybrid PV/battery‐storage unit for residential applications

Under their ‘Gone Green’ deployment scenario, National Grid forecast that energy generated from photovoltaics (PV) in the UK is expected to rise from 2 to 15 GW over the next 20 years. This is being driven by the UK's legal obligations around installing renewable energy sources and cutting greenhouse gases, the rising cost of energy and concerns around the security of supply. Power electronic converters are a key enabling technology for PV and other low-carbon technologies (LCTs). However, the use of LCTs can result in problems for the electrical distribution network such as supply voltage distortion and over-voltages, which threaten to limit or delay their uptake. The project described here is investigating the use of GaN-based converters in a hybrid PV/battery-storage unit for residential applications. The potential for MHz operation of GaN offers smaller, lighter, more efficient, and lower cost converters compared with existing silicon-based units and their deployment could lead to an increase in the installed LCT capacity on the network.

Hardware Implementation of Energy Efficient Deep Learning Neural Network Based on Nanoscale Flash Computing Array

AbstractDeep learning neural network (DNN) can provide efficient approaches to process the increasing unstructured data, such as images, audio, and video. To improve the computing power and the energy efficiency of data processing in DNN, a universal and reconfigurable computing paradigm with the hardware implementation scheme including the convolution, pooling, and fully connected layers is developed based on nanoscale flash computing arrays, which can be massively fabricated. Via precisely tuning the threshold voltage, the fabricated 65 nm nanoscale flash cells can exhibit 16 levels (four bits) of storage states. To confirm the feasibility of the computing paradigm, an exemplary five‐layer DNN is simulated based on the measured data from the nor‐type (NOR) flash memory and exhibits 97.8% recognition accuracy of Modified National Institute of Standards and Technology (MNIST) handwritten digit database with the speed of 4.2 × 105 fps at 104 MHz operating frequency. The proposed paradigm with low energy and chip cost shows great promise for future energy efficient and massively parallel data processing of DNN.