Metal-oxide-semiconductor Field-effect Transistors Research Articles

CNTFET-based SRAM cell design using INDEP technique

As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube field effect transistor (CNTFET) has exhibited remarkable advantages compared to MOSFETs in circuit designs within the nanoscale range, owing to its extraordinary characteristics. In this work, a CNTFET-based six-transistor (6T) static random access memory (SRAM) cell is designed using the low power input-dependent (INDEP) technique. The suggested circuits' performance and efficiency is enhanced using CNTFET technology. The suggested design undergoes circuit simulations using the 32 nm CNTFET Stanford model. The results obtained from the simulations indicate that the suggested INDEP 6T SRAM cell surpasses both the conventional 6T SRAM cell and the previous designs in terms of power dissipation, delay, and energy efficiency. The hold, read, and write operations use less power, and the hold and write operations take less time to complete. The suggested design also demonstrates improved energy efficiency for hold and read operations compared to the conventional design. Furthermore, a stability analysis is conducted on the suggested INDEP 6T SRAM cell using the static noise margin (SNM) metric. The suggested INDEP approach in comparison to the other schemes has greater SNMs for hold, write, and read operations, indicating improved SRAM cell stability.

Evaluation of the chemical states and electrical activation of ultra-highly B-doped Si1-xGex by ion implantation and subsequent nanosecond laser annealing

Given that transistordimensions are approaching atomic scale in metal–oxide–semiconductor field-effect-transistors (MOSFETs), attaining low-contact resistivity (ρc) between contact-metal and Si is a primary challenge for source/drain (S/D) fabrications. To reduce ρc, it is necessary to increase active dopant concentration in the semiconductor region underneath the contact-metal. High-dose ion-implantation and nanosecond laser-annealing (NLA) have been intensively investigated to produce highly activated layers in S/D regions. Particularly for the B-doped SiGe layers, which are used as S/D stressor for p-MOSFETs, non-substitutional B species are generated in the highly doped films at concentrations exceeding ∼ 1021 cm−3. These non-substitutional B are electrically non-activated and thus should be minimized to reduce ρc. In this study, we investigated the chemical states and electrical activation in highly B-doped SiGe layer. Using X-ray photoelectron spectroscopy (XPS), we examined the substitutionality of B-atoms and identified new chemical states of Si-B and Ge-B bonds in Si 2p and Ge 3d peaks. In the B 1s spectra, electrical activation states are determined by quantifying relative area ratios of the active/inactive B peaks, which are well matched with activation rates calculated by Hall measurements. Our findings systematically explained the activation behavior of NLA-treated B-doped SiGe films in high B-concentration ranges.

Performance comparison and analysis of silicon-based and carbon-based integrated circuits under VLSI

Since 1960, the semiconductor industry has invented Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Complementary Metal Oxide Semiconductor (CMOS) technologies. Subsequently, the semiconductor-based integrated circuit industry has led a new generation of information revolution, driving the rapid development of various electronic circuit technologies worldwide. With the physical limitations of the silicon semiconductor process, Moores Law is also approaching its physical limit. In the search for new semiconductor materials, carbon nanotube semiconductors have become one of the candidate materials for new semiconductor materials due to their many advantages, and their many characteristic parameters are even better than those of silicon semiconductors of the same size. This article introduces the research status, performance characteristics, and comparison of silicon-based and carbon-based integrated circuits, as well as the current application scenarios of silicon-based and carbon-based integrated circuits in the industry, and the many problems encountered. Finally, this article analyses the future development direction of the integrated circuit industry and the possible challenges it may face.

A Study on the Design Method of Hybrid MOSFET-CNTFET Based SRAM – A Secondary Publication

More than 10,000 carbon nanotube field-effect transistors (CNTFETs) have been successfully integratedinto one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Thesetransistors offer advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, andtransparency. The three-dimensional multilayer structure of the CNTFET semiconductor chip, along with ongoing researchin CNTFET manufacturing processes, increases the potential for creating a hybrid MOSFET-CNTFET semiconductorchip. This chip combines conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and CNTFETs inone integrated system. This paper discusses a methodology to design 6T binary static random-access memory (SRAM)using a hybrid MOSFET-CNTFET. This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAMby leveraging existing MOSFET SRAM or CNTFET SRAM design approaches. Additionally, this paper compares itsperformance with conventional MOSFET SRAM and CNTFET SRAM designs.

Mechanisms of negative bias instability of commercial SiC MOSFETs observed by current transients

This article explains the mechanisms of negative bias instability in commercial n-channel SiC metal–oxide semiconductor field-effect transistors (MOSFETs) by analysis of transient gate currents. The current–voltage measurements were performed at different temperatures along with capacitance–voltage measurements to characterise hole trapping and de-trapping in planar SiC MOSFETs. The experimental results reveal that near-interface traps (NITs) with energy levels aligned to the valence band trap holes from the valence band by tunneling, which is different from published results about NITs with energy levels aligned to the energy gap. The impact of the aluminium implantation process of the p-type region on hole trapping is also demonstrated. The presented analysis also reveals that the hole trapping by NITs is limited to the p-type region, indicating that the aluminium implantation process is responsible for the detected NITs.

Electrical property improvement for boron-doped diamond metal–oxide–semiconductor field-effect transistors

High-performance boron-doped diamond (B-diamond) metal–oxide–semiconductor field-effect transistors (MOSFETs) are fabricated by improving fabrication process and device structures. Drain current maximum values for the B-diamond MOSFETs operating at room temperature and 300 °C are −1.2 and −10.9 mA/mm, respectively. Both exhibit on/off ratios higher than 109 and their extrinsic transconductance maximum values are 29.0 and 215.7 μS/mm, respectively. These properties surpass the values reported in previous studies.

Enhancement of the Synaptic Performance of Phosphorus-Enriched, Electric Double-Layer, Thin-Film Transistors

The primary objective of neuromorphic electronic devices is the implementation of neural networks that replicate the memory and learning functions of biological synapses. To exploit the advantages of electrolyte gate synaptic transistors operating like biological synapses, we engineered electric double-layer transistors (EDLTs) using phosphorus-doped silicate glass (PSG). To investigate the effects of phosphorus on the EDL and synaptic behavior, undoped silicate spin-on-glass-based transistors were fabricated as a control group. Initially, we measured the frequency-dependent capacitance and double-sweep transfer curves for the metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors. Subsequently, we analyzed the excitatory post-synaptic currents (EPSCs), including pre-synaptic single spikes, double spikes, and frequency variations. The capacitance and hysteresis window characteristics of the PSG for synaptic operations were verified. To assess the specific synaptic operational characteristics of PSG-EDLTs, we examined EPSCs based on the spike number and established synaptic weights in potentiation and depression (P/D) in relation to pre-synaptic variables. Normalizing the P/D results, we extracted the parameter values for the nonlinearity factor, asymmetric ratio, and dynamic range based on the pre-synaptic variables, revealing the trade-off relationships among them. Finally, based on artificial neural network simulations, we verified the high-recognition rate of PSG-EDLTs for handwritten digits. These results suggest that phosphorus-based EDLTs are beneficial for implementing high-performance artificial synaptic hardware.

Development and Fabrication of MOSFET-Based Radiation Dosimeter (RadFET) for Enhanced Performance in Space Missions

This work presents the development and fabrication process of a radiation dosimeter based on Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) technology, known as RadFET. The aim of this study is to determine the specifications of the RadFET sensor for use in space missions by the Egyptian Space Agency in SPNeX mission. We have successfully determined the sensor specifications, specified the required electronic components for readout circuits, and confirmed the correct operation of the RadFET device through device simulations and radiation-induced damage models. The fabrication process was conducted at Zewail City of Science, Technology and Innovation cleanroom facility, utilizing Sentaurus TCAD for device and process simulations. We have conducted fabrication experiments for phosphorus spin-on dopant application, dry oxide growth, and wet oxidation using water vapor bubblers. The dosimeter readout PCB fabrication and assembly phases have been successfully completed. The developed RadFET dosimeter holds great promise for radiation monitoring in space missions, ensuring enhanced safety and reliability of electronic systems.

Smart pH Sensing: A Self-Sensitivity Programmable Platform with Multi-Functional Charge-Trap-Flash ISFET Technology

This study presents a novel pH sensor platform utilizing charge-trap-flash-type metal oxide semiconductor field-effect transistors (CTF-type MOSFETs) for enhanced sensitivity and self-amplification. Traditional ion-sensitive field-effect transistors (ISFETs) face challenges in commercialization due to low sensitivity at room temperature, known as the Nernst limit. To overcome this limitation, we explore resistive coupling effects and CTF-type MOSFETs, allowing for flexible adjustment of the amplification ratio. The platform adopts a unique approach, employing CTF-type MOSFETs as both transducers and resistors, ensuring efficient sensitivity control. An extended-gate (EG) structure is implemented to enhance cost-effectiveness and increase the overall lifespan of the sensor platform by preventing direct contact between analytes and the transducer. The proposed pH sensor platform demonstrates effective sensitivity control at various amplification ratios. Stability and reliability are validated by investigating non-ideal effects, including hysteresis and drift. The CTF-type MOSFETs’ electrical characteristics, energy band diagrams, and programmable resistance modulation are thoroughly characterized. The results showcase remarkable stability, even under prolonged and repetitive operations, indicating the platform’s potential for accurate pH detection in diverse environments. This study contributes a robust and stable alternative for detecting micro-potential analytes, with promising applications in health management and point-of-care settings.

Simulation Research on High-Voltage β-Ga2O3 MOSFET Based on Floating Field Plate

The simulation model of a depletion-mode (D-mode) β-Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET) is constructed by Silvaco ATLAS technology computer-aided design (TCAD) simulation, which employs an epitaxial drift layer grown on a sapphire substrate. On this basis, the floating field plate (F-FP) structure based on the gate-pad-connected field plate (P-FP) is proposed to improve the breakdown characteristics of the device, which is easy to be prepared. The working principle of F-FP is investigated with the help of the device with one F-FP. Based on the principle that the number of floating field plates is increased on an optimized floating field plate structure. Subsequently, the devices with two and three floating field plates are simulated in turn, and the optimal structural parameters of the three F-FPs device are finally obtained, and the breakdown voltage is 3800 V at this time. In addition, it is found that the device breakdown voltage is increased by approximately 500–600 V for each additional floating field plate.

Normally-off recessed gate β-Ga2O3 MOSHFETs with a modulation-doped heterostructure back-barrier

This study demonstrates enhancement-mode recessed-gate β-Ga2O3 metal–oxide–semiconductor heterojunction field-effect transistors (MOSHFETs) with a combination of the MOS channel and a modulation-doped heterostructure to improve maximum drain current and on-resistance (RON). In this proposed device concept, modulation doping in the heterostructure back-barrier inserted into the MOS channel increases the electron density in the MOS channel while maintaining a normally-off operation. First, 2D simulations of enhancement-mode recessed-gate β-Ga2O3 metal–oxide–semiconductor field-effect transistors (MOSFETs) were performed in a Silvaco ATLAS TCAD environment to calibrate the transfer characteristics with the measured data of the investigated device reported previously. Second, using calibrated physical models and parameters, the transfer and transconductance characteristics, and output and off-state characteristics of the enhancement-mode recessed-gate β-Ga2O3 MOSHFETs were comprehensively investigated. The maximum drain current at VGS = 8 V and VDS = 10 V could be increased up to 32.6 mA mm−1 from 9.1 mA mm−1 with the MOSHFET in comparison with that of the recessed-gate MOSFET. The breakdown voltage increased considerably from 186 V to 226 V for the recessed-gate MOSHFET. The proposed device also showed a lower RON, which decreased from 354 Ω.mm to 214 Ω.mm owing to greater electron accumulation in the channel owing to the introduction of the modulation-doped heterostructure.

The Effect of Diluted N2O Annealing Time on Gate Dielectric Reliability of SiC Metal-Oxide Semiconductor Capacitors and Characterization of Performance on SiC Metal-Oxide Semiconductor Field Effect Transistor

We performed dry oxidation on n-type silicon carbide (SiC), followed by annealing in diluted N2O, and subsequently fabricated n-type MOS structures. The study aimed to investigate the impact of different annealing times on the trap charges near the SiC/SiO2 interface and the reliability of the gate dielectric. Capacitance-voltage (C-V) and current-voltage (I-V) measurements of the n-type MOS revealed that increasing the annealing time with N2O effectively reduces the density of electron traps near the SiC/SiO2 interface, mitigates the drift in flat-band voltage and enhances the oxide breakdown field strength. However, excessive annealing time leads to an increase in the flat-band voltage drift of the MOS, resulting in premature oxide breakdown. Using the optimized annealing conditions, we fabricated n-type LDMOSFETs and obtained the threshold voltage (Vth), field-effect mobility (μFE) and specific on-resistance (Ron-sp) from the transfer curve (Id-Vg) and output curve (Id-Vd) measurements. The research findings provide valuable insights for the gate oxidation process of SiC.

A New Zero-Voltage Zero-Current Switching Converter with Minimum Duty Cycle Loss

Zero-voltage zero-current switching (ZVZCS) phase-shifted full-bridge (PSFB) converters have been widely used in high-power applications because of their high efficiency, low price, and easy control. Currently, the biggest problem with PSFB converters in operation is their high duty cycle loss. With the increase in current, duty cycle loss grows and degrades their performance. Focusing on this problem, a new ZVZCS PSFB converter is proposed in this paper. This topology adds an auxiliary circuit to minimize duty cycle loss. Moreover, the lagging-leg switches can obtain zero-current switching (ZCS) easily with the help of the circuit. The auxiliary circuit is built of four metal-oxide-semiconductor field-effect transistors (MOSFETs) and an auxiliary transformer, and extra voltage can be added to the primary coils when the direct-current (DC) voltage is small. This paper discusses its operation principles and characteristics, and an experiment of a 2 kW prototype was conducted, the results of which demonstrate the advantages of the presented circuits.

Advancements And Applications of Field-Effect Transistors in Modern Electronics

Field-Effect Transistors (FETs) have evolved as fundamental semiconductor devices pivotal to modern electronics. This paper provides an extensive overview of FETs, encompassing their definition, classification, and historical development. FETs, such as Junction Field-Effect Transistors (JFETs) and Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), are explained, highlighting their distinct characteristics and applications. Additionally, innovative FET variants like Piezoelectric Field-Effect Transistors (PiezoFETs) and High Electron Mobility Transistors (HEMTs) are explored for their unique attributes and applications. The paper underscores the critical role FETs play in diverse sectors, including low-power digital circuits, RF applications, biosensors, and flexible electronics. It emphasizes their contributions to achieving ultra-low power consumption, rapid analysis, and real-time, label-free diagnostics. The collaborative efforts of experts from various disciplines are emphasized as essential for optimizing FET-based biosensors. Furthermore, the paper emphasizes the exciting potential of graphene-based FETs (G-FETs) in Bioelectronics and their ability to revolutionize point-of-care diagnostics. G-FETs' scalability, low-cost manufacturing, and superior properties make them a promising choice for future healthcare applications.

Compact Spice Models for Terafets

Field effect transistors (FETs) in plasmonic regimes of operation could detect terahertz (THz) radiation and operate as THz interferometers, spectrometers, frequency-to-digital converters and THz modulators and sources. We report on the development of compact models for Si MOS (Metal-Oxide-semiconductor) and heterostructure-based plasmonic FETs (or TeraFETs) suitable for circuit design in the THz range and based on the multi-segment unified charge control model. This model accounts for the electron inertia effect (by incorporating segmented Drude inductances), for the ballistic field effect mobility, which is proportional to the channel length, for parasitic resistances and capacitances and for the leakage current. It is validated by comparison with experimental data and TCAD simulation results. The model can be used for simulation and optimization of sub-THz and THz detectors. Our simulations use up to 200 segments in the device channel. The results are also in good qualitative agreement with the hydrodynamic simulations. Applications of our model could dramatically reduce astronomical design costs of nanoscale VLSI reaching US$1.5 billion for the 3 nm technological node.

Characteristics of β-Ga2O3 MOSFETs on polycrystalline diamond via electrothermal modeling

The integration of polycrystalline diamond (PCD) has been considered as a promising approach for overcoming the thermal management challenges in β-Gallium oxide (β-Ga2O3) metal-oxide-semiconductor field effect transistors (MOSFETs). This study investigates the coupled electrical and thermal characteristics of β-Ga2O3-on-diamond MOSFETs via electrothermal modeling. Results reveal that thicker diamond improves heat transfer efficiency with an optimal value of ∼100 μm by utilizing regions with higher thermal conductivity. The ambient temperature (Tamb) correlates negatively with the device temperature rise (ΔT) due to reduced electrical mobility and current density at elevated temperatures. Excellent electrical performance has been demonstrated for β-Ga2O3 MOSFETs, with a high saturation current density (Id,sat = 42.7 mA/mm) and a low specific on-resistance (RON,sp = 264.8 mΩ·mm2) at 300 K with Vg = −2 V and Vd = 20 V, along with a high on/off ratio (Ion/Ioff ∼ 1011) and a low subthreshold swing (SS = 83.3 mV/dec), making it highly suitable as a power switch. Comparative analysis with devices on other substrates (Si, SiC, and sapphire) highlights the exceptional carrier mobility and heat spreading capability benefited from the diamond substrate, especially at high power levels. Our TCAD-based fully-coupled electrothermal simulations provide comprehensive and accurate insights into the electrical and thermal performance of Ga2O3-based devices, offering guidance for the design and optimization of high-power devices.

Modeling of non-intrinsic noise in nanometer metal oxide semiconductor field effect transistors

With the proportional reduction of metal–oxide–semiconductor field effect transistor (MOSFET) devices, the short channel effect, the parasitic effect, and the field strength effect are significantly enhanced, the proportion of parasitic resistance increases, and the non-intrinsic noise also increases, which seriously affects the working efficiency of the device. However, existing research mainly focuses on the intrinsic noise of MOSFET, and there is little research on the non-intrinsic noise; furthermore, the models describing the relationship between non-intrinsic noise, device structure, and bias have not yet been addressed. Therefore, in this paper, 90, 65, 32, 10, and 5 nm MOSFETs are studied. The rate of the intrinsic ballistic parameter is introduced to set up the source–drain current model and the non-intrinsic noise model. The source–drain current model is consistent with the theoretical model, numerical simulation, and experimental results in the literature. Finally, the relationship between the non-intrinsic noise and the bias and the device parameters are analyzed, and the conclusion is helpful to improve the working efficiency, lifetime, and response speed of nanoscale MOSFET devices.

The Understanding and Compact Modeling of Reliability in Modern Metal-Oxide-Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms.

With the technological scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling.

Improving the Efficiency of an Isolated Bidirectional Dual Active Bridge DC–DC Converter Using Variable Frequency

This article presents a control method for an isolated bidirectional dual active bridge DC–DC converter (IBDC) where single phase shift (SPS) and variable frequency (VF) modulations are combined simultaneously with the purpose of improving the efficiency of the converter applied to the bidirectional charging of electric vehicles batteries. A complete power characterization of the dual active bridge (DAB) converter is carried out. The combined control achieves lossless turn-on and turn-off on the primary bridge for a wide range of output powers. A comparative study of power losses between the traditional SPS control and the combined method proposed here was also carried out. A prototype with an output power of 10 kW was built based on Silicon Carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFET), with which a peak efficiency close to 99% was obtained, thus verifying the viability of the method.

Circuit simulation-based comparison of power electronics devices in a five-level converter for UAV applications

<p>In this paper, the performance of a 5-level cascaded H-bridge inverter in unmanned aerial vehicle (UAV) applications is analized to identify, at the converter design stage, the better device choice depending on different UAV operation scenarios. Considering that regardless of the specific application there are some typical operations, such as take-off, climb, land, cruise, and potential recurring climbs and descents, the results can support the choice by considering the typical working conditions of the specific application where the UAV would be used. The results have been obtained by simulating the H-bridge inverter considering the circuit models of insulated-gate bipolar transistors (IGBTs), GaN high-electron-mobility transistors (HEMTs), and Si and SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) provided by manufacturers. The study has highlighted that the choice of the device depends on the UAV usage, switching frequency, and load conditions. More specifically, considering the typical devices and systems costs in the case of a selective harmonic elimination procedure operating at the fundamental switching frequency, the Si devices should be used. Moreover, the preference for using IGBTs or Si MOSFETs depends on the typical working conditions of the UAV application. In the case of phase-shift carrier modulation technique, at 4 kHz the MOSFET is the best device and the choice between Si and SiC devices depends on the UAV application's main operation scenarios. At 20 kHz the SiC MOSFET is the best device, while at higher frequencies the GaN HEMT cost should be faced to take advantage of its best performance.</p>