Metal Interconnect Lines Research Articles

A Mechanistic Model for Plastic Metal Line Ratcheting Induced BEOL Cracks in Molded Packages

Metal line ratcheting and passivation cracking in back-end-of-line (BEOL) structures are significant reliability concerns for molded packages that are in widespread use at the present time. When metal lines plastically deform due to ratcheting, the passivation overcoat accumulates stress at the corner upon temperature cycling and is eventually susceptible to fracture. Since packaging materials’ interaction with the die is the cause of the failure, the problem is inherently multiscale in nature requiring the analysis model to span from package dimension to BEOL length scale. In this article, the mechanistic cause for stress accumulation is elucidated. Furthermore, a global–local modeling strategy is applied to model the passivation crack initiation and growth. A global model with coarse mesh was built of the package. The local region around the interconnect metal line in the die was modeled using boundary conditions extracted from the global model. A novel load decomposition technique is developed to identify the loading mode that best correlates with the experimentally observed fracture. It is shown that shear is the dominant loading mode inducing the observed die cracks. Furthermore, it is demonstrated that the thermal expansion mismatch between the mold compound and the lead frame with the silicon die induces the shear load on the BEOL structure. Due to the fact that mold compound is applied at a temperature that is higher than that seen during thermal cycling, the direction of the induced shear load is constant regardless of whether the package is heated or cooled. As the metal line plastically yields during every temperature cycle, the plastic deformation ratchets or accumulates in the same direction over the course of the thermal cycling test. The yielding of metal line results in stiffness reduction, leading to steady accumulation of stress in the passivation corner, causing it to fracture eventually.

A Flexible Design Platform for Si/SiGe Exchange-Only Qubits with Low Disorder.

Spin-based silicon quantum dots are an attractive qubit technology for quantum information processing with respect to coherence time, control, and engineering. Here we present an exchange-only Si qubit device platform that combines the throughput of CMOS-like wafer processing with the versatility of direct-write lithography. The technology, which we coin "SLEDGE", features dot-shaped gates that are patterned simultaneously on one topographical plane and subsequently connected by vias to interconnect metal lines. The process design enables nontrivial layouts as well as flexibility in gate dimensions, material selection, and additional device features such as for rf qubit control. We show that the SLEDGE process has reduced electrostatic disorder with respect to traditional overlapping gate devices with lift-off metallization, and we present spin coherent exchange oscillations and single qubit blind randomized benchmarking data.

Ab initio screening of metallic MAX ceramics for advanced interconnect applications

The potential of a wide range of layered ternary carbide and nitride Mn+1AXn [an early transition metal (M), an element of columns 13 or 14 of the periodic table (A), and either C or N (X)] phases as conductors in interconnect metal lines in advanced complementary metal-oxide-semiconductor (CMOS) technology nodes has been evaluated using automated first-principles simulations based on density-functional theory. The resistivity scaling potential of these compounds, i.e., the expected sensitivity of their resistivity to reduced line dimensions, has been benchmarked against Cu and Ru by evaluating their transport properties within a semiclassical transport formalism. In addition, their cohesive energy has been assessed as a proxy for the resistance against electromigration and the need for diffusion barriers. The results indicate that numerous MAX phases show promise as conductors in interconnects of advanced CMOS technology nodes.

A novel airgap formation scheme by GO nanosheet gap sealing process with extreme low effective dielectric constant

In order to reduce the parasitic capacitance between the interconnect metal line, low-k material was developed and integrated into CMOS BEOL process, and airgap is the ultimate low-k material with the lowest dielectric constant close to 1. In this work, a novel airgap formation scheme was proposed to form the airgap by low-cost coating process, in which Graphene Oxide (GO) nanosheet was used as gap-filling suppressor to seal the gap between two adjacent metal line and form the airgap. Traditional non-conformal CVD gap sealing process was firstly developed and compared with the proposed scheme. It was found that the non-conformal CVD sealing process cannot achieve high performance airgap, and there will always be some material deposited into the gap between the metal interconnect line even for very narrow gap. For the proposed scheme, volume ratio of GO sealed airgap to gap region before sealed can reach to about 85% with much wider gap, and calculated effective relative dielectric constant of this region is about 1.57. When increasing the gap CD to value larger than GO nanosheet size, conformal film deposition can be got, which indicate that GO nanosheet with the size larger than gap CD can seal the gap in the very beginning and prevent further material depositing into the gap to make the large ratio airgap formation.

Vapor-deposited zeolitic imidazolate frameworks as gap-filling ultra-low-k dielectrics

The performance of modern chips is strongly related to the multi-layer interconnect structure that interfaces the semiconductor layer with the outside world. The resulting demand to continuously reduce the k-value of the dielectric in these interconnects creates multiple integration challenges and encourages the search for novel materials. Here we report a strategy for the integration of metal-organic frameworks (MOFs) as gap-filling low-k dielectrics in advanced on-chip interconnects. The method relies on the selective conversion of purpose-grown or native metal-oxide films on the metal interconnect lines into MOFs by exposure to organic linker vapor. The proposed strategy is validated for thin films of the zeolitic imidazolate frameworks ZIF-8 and ZIF-67, formed in 2-methylimidazole vapor from ALD ZnO and native CoOx, respectively. Both materials show a Young’s modulus and dielectric constant comparable to state-of-the-art porous organosilica dielectrics. Moreover, the fast nucleation and volume expansion accompanying the oxide-to-MOF conversion enable uniform growth and gap-filling of narrow trenches, as demonstrated for 45 nm half-pitch fork-fork capacitors.

3D wafer level packaging technology based on the co-planar Au–Si bonding structure

Driven by ever-growing demands on 3D integration, various state-of-the-art electronics packaging techniques have been developed. This study presents a novel and cost-efficient 3D wafer level packaging technology based on co-planar Au–Si bonding structures, whose two remarkable features are (1) eliminating the height difference derived from multi-layer metal interconnection lines crossing bonding rings by building co-planar bonding structures and (2) accomplishing vertical interconnections of low-resistivity Si column structures by forming Au–Si bonding ohmic contacts. In this paper, the packaging structure is interpreted by designs, fabrications and tests, in which the efficiency verification on co-planar bonding structures and vertical interconnections is concretely addressed. The performances on co-planar bonding structures have been revealed by 3D profiles of bonding surfaces, cross-sectional SEM images (the gap-free bonding layer) and tensile tests for Au–Si bonding strength. Besides, tests on leak rates of packaged chips indicate good packaging hermeticity. In terms of vertical interconnection properties, an in situ extracting method on the specific contact resistance (ρc) is also introduced to quantitatively appraise the quality of Au–Si ohmic contacts. Therefrom, the measured resistance of a vertical interconnection (~1 Ω) could be qualified for most devices’ interconnection requirements. And further, the extracted ρc values of 1.83–3.48 × 10−8 Ω · m2 also imply forming of good ohmic contacts in Au–Si bonding. More importantly, being analogously conducted by any available eutectic bonding techniques, this 3D packaging method has inherently extensive application prospects.

Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS⁻NEM Hybrid Circuits.

Considering the isotropic release process of nanoelectromechanical systems (NEMSs), defining the active region of NEM memory switches is one of the most challenging process technologies for the implementation of monolithic-three-dimensional (M3D) CMOS–NEM hybrid circuits. In this paper, we propose a novel encapsulation method of NEM memory switches. It uses alumina (Al2O3) passivation layers which are fully compatible with the CMOS baseline process. The Al2O3 bottom passivation layer can protect intermetal dielectric (IMD) and metal interconnection layers from the vapor hydrogen fluoride (HF) etching process. Thus, the controllable formation of the cavity for the mechanical movement of NEM devices can be achieved without causing any damage to CMOS baseline circuits as well as metal interconnection lines. As a result, NEM memory switches can be located in any place and metal layer of an M3D CMOS–NEM hybrid chip, which makes circuit design easier and more volume efficient. The feasibility of our proposed method is verified based on experimental results.

Cu/Cu Barrier Interconnect with Low Resistivity for the Application to the Next-Generation and High-Resolution Display Fabricated Using Microwave-Assisted Sputter

Displays with large size and high resolution are required in many electronic devices such as mobile phones, notebooks, and televisions. In recent times, 8k ultra-high-definition (UHD) display which will be the standards of next-generation display has been developed. While the demand for displays with high-pixel-density is increasing, it is difficult to increase the resolution because of resistor-capacitor (RC) delay issue. The resistance is increased with the display size due to the length of metal lines. When the resolution is increased, the capacitance of metal lines is also increased because of the number of crossings of metal lines. The meaning of RC delay is the signal delay through the circuit wiring as a result of resistance and capacitance effects. This increase induces the severe electrical loads on the gate and data lines. Therefore, controlling these two effects is the major challenge in making high-resolution display. To minimize the effect of the RC delay, many researchers have been studied the variety of materials which can be used in a metal interconnect lines. There are lots of materials such as Al, Mo, W, Cu, and Ti. Among these materials, copper is the most suitable candidate because it has lower resistivity than aluminum, which has been used as conventional interconnect material. Using a material with low resistivity like copper can reduce the RC delay, in other words, increase the electrical signal speed through the metal lines. Although the copper has a resistivity of 1.7 μΩ∙cm, it shows 2.1 ~ 2.3 μΩ∙cm within the thickness of 1 μm when deposited using DC/RF sputtering method. This is due to the fact that it is difficult to deposit high-quality copper film by using the conventional sputtering method. To overcome these problems, we employed microwave-assisted sputter (MWA sputter), providing high-quality copper films having the resistivity of 1.95 μΩ∙cm within the thickness of 1 μm even after formation of the metal lines. The MWA sputtering is an enhanced sputtering method using electron cyclotron resonance (ECR) phenomenon with the induction of microwave into the DC magnetron sputtering. The MWA sputtering has the advantage of generating highly ionized plasma, having low discharge voltage and low working pressure. Therefore, we can deposit high quality copper film by using MWA sputtering, enabling the reducing RC delay for next-generation display. However, when we deposit copper, the barrier metal is always needed because the copper can easily diffuse into adjacent materials. Unless suitable barrier material is used, it can be cause of degradation of device performance. For these reasons, we fabricated Cu/Cu barrier interconnect as a source/drain electrode and observed various properties including calculation of resistivity. In this study, we report a study of properties of copper film deposited by DC sputtering and MWA sputtering using scanning electron microscope (SEM), x-ray diffraction spectroscopy (XRD) and atomic force microscope (AFM). The film stress was calculated before and after the formation of the Cu/Cu barrier metal line because film stress is an important parameter when fabricating electronic devices. Mo and Mo-Ti alloy was used as the copper barrier metal and we developed wet etching condition of Cu/Cu barrier interconnect. After the etching process, we measured etching profile using SEM cross-section image and calculate taper angle. Consequently, we obtained resistivity of Cu/Cu barrier interconnect deposited by DC sputtering and MWA sputtering, respectively. It revealed that Cu/Cu barrier interconnect deposited by MWA sputtering shows the lower resistivity than by DC sputtering. From the experimental results, we confirmed that MWA sputtering method makes it possible to deposit high quality metal films with low resistivity, which gives new opportunities for the design and realization of next-generation displays. Reference [1] Y. Goh, J. Ahn, J.R. Lee, W.W. Park, S.-H K Park and S Jeon. ACS Appl. Mater. Interfaces., 2017, 9 (42), pp 36962-36970

Defect localization of metal interconnection lines in 3-dimensional through-silicon-via structures by differential scanning photocapacitance microscopy

We report a differential scanning photocapacitance microscopy technique based on the detection of light-induced capacitance changes allowing mapping of metal interconnection line defects in through-silicon-via (TSV) structures used in three-dimensional (3-D) integration technology. Due to the photosensitive silicon depletion capacitance, observation of the photocapacitance response enables non-destructive two-dimensional (2-D) visualization of metallization line ruptures in TSV structures. We demonstrate the application of the proposed method on a TSV chain structure and reveal the location of the open metallization rupture.

25‐5: Distinguished Student Paper: Fully‐Integrated Active Matrix Programmable UV and Blue Micro‐LED Display System‐on‐Panel (SoP)

High pixel per inch (PPI) and high resolution micro‐LED (μLED) displays are attracting more and more attentions. The increasing pixel number requires a large amount of bonding pads and brings huge difficulties to micro‐LED system design and lowers power efficiency as well. It is urgent to integrate row and column driving circuits onto the micro‐LED panel. Here we report a fully integrated active matrix programmable micro‐LED system on panel (SoP) with ultraviolent (UV) and blue emission wavelengths. The micro‐LED SoP has a resolution of 60x60 and pixel pitch of 70μm. The micro‐LED SoP was achieved by integrating micro‐LED arrays with silicon‐based PMOS driving panel using fine‐toned flip‐chip bonding technology. With fully integrated scan and data circuits, the number of bonding pads was greatly reduced from 136 to 28 and large amount of metal interconnection lines were saved. The micro‐LED SoP panel was mounted on a periphery driving board and representative characters were displayed successfully.

Fully-integrated active matrix programmable UV and blue micro-LED display system-on-panel (SoP)

High pixel per inch and high-resolution micro-LED displays are attracting more and more attentions. The increasing pixel number requires a large amount of bonding pads and brings huge difficulties to micro-LED system design and lowers power efficiency as well. It is urgent to integrate row and column driving circuits onto the micro-LED panel. Here, we report a fully integrated active matrix programmable micro-LED system on panel (SoP) with ultraviolet and blue emission wavelengths. The micro-LED SoP has a resolution of 60 × 60 and pixel pitch of 70 μm. The micro-LED SoP was achieved by integrating micro-LED arrays with silicon-based p-channel metal-oxide semiconductor driving panel using fine-toned flip-chip bonding technology. With fully integrated scan and data circuits, the number of bonding pads was greatly reduced from 136 to 28, and large amount of metal interconnection lines were saved. The micro-LED SoP panel was mounted on a periphery driving board, and representative characters were displayed successfully.

Transient Heat Conduction in On-Chip Interconnects Using Proper Orthogonal Decomposition Method

A major challenge in maintaining quality and reliability in today's microelectronics chips comes from the ever increasing levels of integration in the device fabrication, as well as from the high current densities. Transient Joule heating in the on-chip interconnect metal lines with characteristic sizes of tens of nanometer, can lead to thermomechanical fatigue and failure due to the thermal expansion coefficient mismatch between different materials. Full-field simulations of nearly a billion interconnects in a modern microprocessor are infeasible due to the grid size requirements. To prevent premature device failures, a rapid predictive capability for the thermal response of on-chip interconnects is essential. This work develops a two-dimensional (2D) transient heat conduction framework to analyze inhomogeneous domains, using a reduced-order modeling approach based on proper orthogonal decomposition (POD) and Galerkin projection. POD modes are generated by using a representative step function as the heat source. The model rapidly predicted the transient thermal behavior of the system for several cases, without generating any new observations, and using just a few POD modes.

Postvoiding Stress Evolution in Confined Metal Lines

Electromigration (EM)-induced voiding is an important reliability concern in modern integrated circuits. Resistance degradation in interconnect metal lines caused by voiding was studied in this paper theoretically by solving the continuity equation describing the stress evolution caused by growing void. A rigid confinement surrounding a metal line makes inapplicable an approximation of the line edge drift for modeling the void volume evolution unless a line is in a stress-free equilibrium state caused by the presence of a saturated void. Derived analytical solution to the continuity equation with a voidless initial condition provides drastically different stress evolution kinetics in comparison with the case of the line edge drift model. It demonstrates that a large stress gradient, which was developed between the surface of a void precursor (flaw) and a metal, becomes a major driving force for the atom migration from the void surface to the metal. In this case, the initial evolution of the void volume does not depend on the electric current density contrary to the case of the line edge drift approximation characterized by the linear dependence of the void growth rate on the current density. At long time limit, the derived solution provides the same kinetics and the steady state with the stress linearly distributed along the line as in the case of preexisted void. The proposed model results much faster kinetics of the void growth and the line resistance degradation than the line edge drift approximation. Void nucleation time can be employed as a reasonable approximation of the EM-induced time to failure in the confined metal line.

Frequency-dependent failure mechanisms of nanocrystalline gold interconnect lines under general alternating current

Thermal fatigue failure of metallization interconnect lines subjected to alternating currents (AC) is becoming a severe threat to the long-term reliability of micro/nanodevices with increasing electrical current density/power. Here, thermal fatigue failure behaviors and damage mechanisms of nanocrystalline Au interconnect lines on the silicon glass substrate have been investigated by applying general alternating currents (the pure alternating current coupled with a direct current (DC) component) with different frequencies ranging from 0.05 Hz to 5 kHz. We observed both thermal fatigue damages caused by Joule heating-induced cyclic strain/stress and electromigration (EM) damages caused by the DC component. Besides, the damage formation showed a strong electrically-thermally-mechanically coupled effect and frequency dependence. At lower frequencies, thermal fatigue damages were dominant and the main damage forms were grain coarsening with grain boundary (GB) cracking/voiding and grain thinning. At higher frequencies, EM damages took over and the main damage forms were GB cracking/voiding of smaller grains and hillocks. Furthermore, the healing effect of the reversing current was considered to elucidate damage mechanisms of the nanocrystalline Au lines generated by the general AC. Lastly, a modified model was proposed to predict the lifetime of the nanocrystalline metal interconnect lines, i.e., that was a competing drift velocity-based approach based on the threshold time required for reverse diffusion/healing to occur.

(Invited) Scanning Probe Microscopes for Subsurface Imaging

Scanning probe microscopes (SPMs) have remarkable sensitivity to the surface. The scanning tunneling microscope, for example, is sensitive to tunneling between the tip and the first few atomic layers of the surface. However, SPMs that measure quantities due to surface potential (scanning Kelvin force microscopy, SKFM), magnetic field (magnetic force microscopy, MFM), or capacitance (scanning capacitance microscopy, SCM) can be sensitive to the electrical properties of regions many micrometers from the terminal tip location. This ability to gather information from a large volume opens up the possibility of extending the range of SPMs into the subsurface of materials.We are trying to image subsurface metal lines in an insulating matrix from their potential via SKFM and via their current density/ magnetic fields via MFM. Towards this end we have produced two test chips. One containing isolated metal lines and squares of Cr, Al, or Au [1] and a second containing metal interconnect lines buried within an insulator at 4 discrete depths. The buried metal lines can be biased to produce various patterns of electric or magnetic field that can be imaged at the surface with the appropriate SPM. The test chip has been designed so that the bonding pads are to one side, leaving clearance for the active regions to be probed with a cantilevered SPM probe.Various test structures from this chip have been simulated with a simple analytical model and with the COMSOL Multiphysics software. Basic simulation geometry consists of three metal lines, 1.2-μm in width, separated by 1.2 μm, and buried beneath an insulating layer of varying depth. COMSOL was utilized to simulate the potential at the surface of the insulator. This potential should be measurable with the scanning Kelvin force microscope. While quite sharp transitions in the surface potential are observed for the basic structure, insertion of a probe with the shape of a real SKFM probe into the simulation substantially dampens the spatial resolution. This result emphasizes the need for high aspect probes and advanced Kelvin force imaging to adequately resolve buried conductors with an insulating matrix [2]. Similar simulations were conducted of the magnetic field due to various current densities.The other test structure used in this work consists of isolated metal lines and squares with different work functions. While relatively large, these structures are helping us determine the ability of SKFM to detect the subsurface structure of nano-composites of conducting particles within an insulating matrix.A complimentary set of experiments is also underway to investigate the ability of SPMs to image insulators buried within conducting matrices. In this work, the scanning microwave microscope (SMM) is being used to detect voids and buried insulating lines in metal. The SMM couples a vector network analyzer to an AFM tip [3]. The reflected s11microwave signal over the frequency range from 0.01 GHz to 18 GHz can be examined. Subsurface imaging with this technique is possible due to variations of the skin depth with frequency [4]. For many metals the skin depth varies from around 1 μm to 50 μm over this frequency range. A desired application of this work is the ability to detect and image voids in through silicon vias (TSVs) for three-dimensional integrated circuits.

Role of Ti and Pt electrodes on resistance switching variability of HfO2-based Resistive Random Access Memory

This paper deals with the role of platinum or titanium–titanium nitride electrodes on variability of resistive switching characteristics and electrical performances of HfO2-based memory elements. Capacitor-like Pt/HfO2 (10nm)/Pt and Ti/HfO2 (10nm)/TiN structures were fabricated on top of a tungsten pillar bottom electrode and integrated in-between two interconnect metal lines. First, quasi-static measurements were performed to apprehend the role of electrodes on electroforming, set and reset operations and their corresponding switching parameters. Memory elements with Pt as top and bottom electrodes exhibited a non-polar behavior with sharp decrease of current during reset operation while Ti/HfO2/TiN capacitors showed a bipolar switching behavior, with a gradual reset. In a second step, statistical distributions of switching parameters (voltage and resistance) were extracted from data obtained on few hundreds of capacitors. Even if the resistance in low resistive state and reset voltage was found to be comparable for both types of electrodes, the progressive reset operation observed on samples with Ti/TiN electrodes led to a lower variability of resistance in high resistive state and concomitantly of set voltage. In addition Ti–TiN electrodes enabled gaining: (i) lower forming and set voltages with significantly narrower capacitor-to-capacitor distributions; (ii) a better data retention capability (10years at 65°C instead of 10years at 50°C for Pt electrodes); (iii) satisfactory dynamic performances with lower set and reset voltages for ramp speed ranging from 10−2 to 107V/s. The significant improvement of switching behavior with Ti–TiN electrodes is mainly attributed to the formation of a native interface layer between HfO2 oxide and Ti top electrode.

Ultra high density three dimensional capacitors based on Si nanowires array grown on a metal layer

We report the fabrication and the characterization of chemical vapor deposition (CVD) grown silicon nanowires capacitors using a complementary-metal-oxide-semiconductor (CMOS) circuit interconnect level compatible process. Silicon nanowires have been grown by CVD on metallic interconnect lines used in today’s CMOS circuits at low temperature (<425 °C) and using copper as catalyst. The nanowire assembly develops a huge surface leading to very high measured capacitance densities reaching 18 μF/cm2, and featuring a ×23 gain when compared to the same structure without nanowires. This opens the path toward embedded capacitances technologies by using bottom-up nanowires.

Crack prevention of highly bent metal thin films in woven electronic textiles

Recent smart textile fabrication methods that are aimed at increasing the integration of electronics with textiles have involved fabricating micro-electronic components directly at the yarn level. Our approach to creating smart textiles is to fabricate thin-film devices and interconnects on plastic strips to create ‘e-fibers’ and weave them into a textile using a commercial weaving machine. e-Fibers are exposed to bending radii as small as 165 μ m during weaving. If patterned interconnect lines and device layers on the surface of the e-fiber are not designed correctly, they will crack due to the high strain and lose their electronic functionality. Brittle sensor and transistor device layers may be protected locally using rigid encapsulation materials, but cracking remains an issue for long metal interconnect lines which require flexibility. We investigated two strain-control methods to prevent the thin-film interconnect lines from cracking during weaving: (1) patterning the metal interconnect lines with a geometric design to slow propagation and merging of cracks and (2) encapsulation of interconnect lines to shift the deposited films to the neutral plain of the substrate. The mechanical behavior of interconnect lines exposed to tensile bending was studied by measuring the change in interconnect resistance versus bending radii ranging from 5 mm to 50 μ m. The critical bending radius, X C , defined as the radius at which the normalized interconnect resistance changes to 1.1 (indicating the onset of film rupturing) was 150 μ m for standard interconnect lines. Patterned interconnect lines had a radius X C of 115 μ m while encapsulated interconnect lines never reached this critical bending radius and showed a maximum resistance change of 1.02 at 100 μ m. These results show that it is possible to design interconnect lines with reduced cracking behavior when exposed to high strain during commercial weaving.

Scaling of reliability of gold interconnect lines subjected to alternating current

We present an investigation of damage morphologies of small-scale gold interconnect lines subjected to thermal fatigue strain generated by alternating current. Fractal dimension analysis reveals a general scaling relation between the critical strain range causing thermal fatigue damage and the ratio of the width to the thickness of the metal line. Such the scaling rule may be useful in controlling reliability of the metal interconnect lines subjected to long-term thermal cyclic strain.

A comparative evaluation of de‐embedding methods for on‐wafer RF CMOS inductor S‐parameter measurements

AbstractThe impact of existing de‐embedding methods applied on on‐wafer RF s‐parameter measurements to evaluate the characteristics of CMOS integrated inductors is examined. Probe pad and metal interconnect line associated parasitic elements need to be removed (de‐embedded) from on‐wafer measurements of inductors fabricated on silicon substrates for proper evaluation of inductor characteristics, such as inductance, quality factor and resonance frequency. For this purpose a chip was fabricated in 0.5 μm CMOS TM1P twin‐tub AMIS technology (Figure 1), with octagonal and spiral inductors and various types of dummy structures, such as different types of open, and short structures as well as a thru structure. The dummy structures are necessary in order to extract the parasitic element components. The Device‐under‐Test (DUT) was a 3.5 turn octagonal inductor of line width 12 μm, spacing 2 μm and external diameter of 160 μm. Existing de‐embedding methods include the open‐short de‐embedding method, a three‐step de‐embedding method, a pads‐short‐open (psod), and a modified four‐step de‐embedding method. These methods have been tested mostly for small devices such as MOS transistors. The impact of each de‐embedding method on inductor characteristics extraction is evaluated and results show differences in the order of 36% for the value of peak quality factor and a maximum difference of 9% for the resonance frequency. The comparative evaluation of the existing de‐embedding methods is based on results extracted from measured S‐parameter data for measurements up to 20 GHz, as well as on results obtained by using the HFSS EM simulator. Based on the results, the modified four‐step method is the most accurate method, and a discussion of improvements to further increase the accuracy of the de‐embedding is done, for a precise characterization of the DUT. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)