A comparative evaluation of de‐embedding methods for on‐wafer RF CMOS inductor S‐parameter measurements

Abstract

AbstractThe impact of existing de‐embedding methods applied on on‐wafer RF s‐parameter measurements to evaluate the characteristics of CMOS integrated inductors is examined. Probe pad and metal interconnect line associated parasitic elements need to be removed (de‐embedded) from on‐wafer measurements of inductors fabricated on silicon substrates for proper evaluation of inductor characteristics, such as inductance, quality factor and resonance frequency. For this purpose a chip was fabricated in 0.5 μm CMOS TM1P twin‐tub AMIS technology (Figure 1), with octagonal and spiral inductors and various types of dummy structures, such as different types of open, and short structures as well as a thru structure. The dummy structures are necessary in order to extract the parasitic element components. The Device‐under‐Test (DUT) was a 3.5 turn octagonal inductor of line width 12 μm, spacing 2 μm and external diameter of 160 μm. Existing de‐embedding methods include the open‐short de‐embedding method, a three‐step de‐embedding method, a pads‐short‐open (psod), and a modified four‐step de‐embedding method. These methods have been tested mostly for small devices such as MOS transistors. The impact of each de‐embedding method on inductor characteristics extraction is evaluated and results show differences in the order of 36% for the value of peak quality factor and a maximum difference of 9% for the resonance frequency. The comparative evaluation of the existing de‐embedding methods is based on results extracted from measured S‐parameter data for measurements up to 20 GHz, as well as on results obtained by using the HFSS EM simulator. Based on the results, the modified four‐step method is the most accurate method, and a discussion of improvements to further increase the accuracy of the de‐embedding is done, for a precise characterization of the DUT. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)