3D wafer level packaging technology based on the co-planar Au–Si bonding structure

Abstract

Driven by ever-growing demands on 3D integration, various state-of-the-art electronics packaging techniques have been developed. This study presents a novel and cost-efficient 3D wafer level packaging technology based on co-planar Au–Si bonding structures, whose two remarkable features are (1) eliminating the height difference derived from multi-layer metal interconnection lines crossing bonding rings by building co-planar bonding structures and (2) accomplishing vertical interconnections of low-resistivity Si column structures by forming Au–Si bonding ohmic contacts. In this paper, the packaging structure is interpreted by designs, fabrications and tests, in which the efficiency verification on co-planar bonding structures and vertical interconnections is concretely addressed. The performances on co-planar bonding structures have been revealed by 3D profiles of bonding surfaces, cross-sectional SEM images (the gap-free bonding layer) and tensile tests for Au–Si bonding strength. Besides, tests on leak rates of packaged chips indicate good packaging hermeticity. In terms of vertical interconnection properties, an in situ extracting method on the specific contact resistance (ρc) is also introduced to quantitatively appraise the quality of Au–Si ohmic contacts. Therefrom, the measured resistance of a vertical interconnection (~1 Ω) could be qualified for most devices’ interconnection requirements. And further, the extracted ρc values of 1.83–3.48 × 10−8 Ω · m2 also imply forming of good ohmic contacts in Au–Si bonding. More importantly, being analogously conducted by any available eutectic bonding techniques, this 3D packaging method has inherently extensive application prospects.