Metal Oxide Silicon Field Effect Research Articles

Piezo-VFETs: Vacuum Field Emission Transistors Controlled by Piezoelectric MEMS Sensors as an Artificial Mechanoreceptor with High Sensitivity and Low Power Consumption.

As one of the most promising electronic devices in the post-Moore era, nanoscale vacuum field emission transistors (VFETs) have garnered significant attention due to their unique electron transport mechanism featuring ballistic transport within vacuum channels. Existing research on these nanoscale vacuum channel devices has primarily focused on structural design for logic circuits. Studies exploring their application potential in other vital fields, such as sensors based on VFET, are more limited. In this study, for the first time, the design of a vacuum field emission transistor (VFET) coupled with a piezoelectric microelectromechanical (MEMS) sensing unit is proposed as the artificial mechanoreceptor for sensing purposes. With a negative threshold voltage similar to an N-channel depletion-mode metal oxide silicon field effect transistor, the proposed VFET has its continuous current tuned by the piezoelectric potential generated by the sensing unit, amplifying the magnitude of signals resulting from electromechanical coupling. Simulations have been conducted to validate the feasibility of such a configuration. As indictable from the simulation results, the proposed piezoelectric VFET exhibits high sensitivity and an electrically adjustable measurement range. Compared to the traditional combination of piezoelectric MEMS sensors and solid-state field effect transistors (FETs), the piezoelectric VFET design has a significantly reduced power consumption thanks to its continuous current that is orders of magnitude smaller. These findings reveal the immense potential of piezoelectric VFET in sensing applications, building up the basis for using VFETs for simple, effective, and low-power pre-amplification of piezoelectric MEMS sensors and broadening the application scope of VFET in general.

Adiabatic Power Management Techniques for Metal Oxide Silicon Field Effect Transistors in Digital Logic Circuits

Metal Oxide Silicon Field Effect Transistors are foundational components in electronics, mainly digital logic circuits. Effective power management in MOSFET-based logic circuits becomes more crucial as technology expands to sub-100-nanometer nodes. Four optimization techniques to reduce power losses during switching transitions are carefully examined in this article. With the first method, QSSERL, no additional timing control clocks are required, which results in significant energy savings, especially in high-frequency applications. In the second method, DFAL, split-level sinusoidal power clocks are used instead of diodes, significantly lowering voltage differentials and power dissipation. Building on DFAL, IDFAL employs control transistors to reduce leakage power, significantly lowering power dissipation and facilitating charge recovery. Lastly, FSOA, inspired by natural species' collective behaviour, enhances key components within MOSFET-based circuits. This paper examines numerous adiabatic logic topics. Developing energy-efficient MOSFET-based logic circuits is essential for improving electronics and satisfying the growing demand for energy-conscious technologies.

A 211-to-263-GHz Dual-LC-Tank-Based Broadband Power Amplifier With 14.7-dBm P SAT and 16.4-dB Peak Gain in 130-nm SiGe BiCMOS

This article presents a broadband sub-terahertz (THz) power amplifier (PA) with a low-loss four-way power combiner. The proposed power combiner consists of an improved zero-degree combiner (ZDC) and a three-conductor Marchand balun simultaneously achieving broadband matching and power combining. The proposed three-conductor Marchand balun adopts a dual- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> tank technique by merging two resonators, and it can be equivalent to a transformer-based multi-resonating network. The power distribution is realized by one input power splitter generating two pairs of differential signals and two parallel 1-to-2 active power splitters. This hybrid distribution driving network further enhances efficiency and power gain. Based on these improvements, a high-output-power sub-THz PA with superior efficiency has been fabricated in the 130-nm SiGe bipolar complementary metal oxide silicon field effect transistor (BiCMOS) technology. The three-stage PA achieves a peak power gain of 16.4 dB, 3-dB small-signal gain bandwidth of 52 GHz from 211 to 263 GHz, a measured maximum saturated output power of 14.7 dBm at 224 GHz, and a peak power-added efficiency (PAE) of 3.13% at 220 GHz. The folded input splitter and extremely compact power combining methodology lead to a core area of 770 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times \,\,280\,\,\mu \text{m}$ </tex-math></inline-formula> .

A Study on the Electric Characteristics of the Trench Gate Field Stop Insulated Gate Bipolar Transistor Through Two-Step Field Stop

Insulated gate bipolar transistor (IGBT) element is an electrically conductive device with Bipolar junction transistor (BJT) output and Metal Oxide Silicon Field Effect Transistor (MOSFET) input. The IGBTs is a power semiconductor device that aims for high breakdown voltage, low on-state voltage, fast switching and reliability. This paper is, the experiment was conducted with a two-step field stop, IGBT instead of a traditional one step field stop. In order to minimize the energy loss caused by the trade-off relationship between breakdown voltage and the on-state voltage drop, the experiment was conducted by forming a two-step field stop. Through concentration control between steps, breakdown voltage, On-state Voltage drop and turn off time could be adjusted in detail, and efficient characteristic values could be obtained accordingly. Experiments have confirmed that the On state voltage drop and turn-off time, in particular, can be adjusted by small failure voltage loss upon change in the first stage field stop.

A New Low Cost Current Measurement Circuit with Temperature Compensation

The electrical characterization of semiconductors devices, when submitted to ionizing radiation should be done in a large range of currents; however, the instrumentation with this ability is very expensive. This work proposes a low-cost circuit using commercial off-the-shelf components (COTS) that enables the measurement of electrical currents in the order of pA range. The circuit presents an output current that is an amplified version of the current to be measured, using the exponential relationship between currents and voltages in Bipolar Junction Transistors (BJTs) and Metal Oxide Silicon Field Effect Transistors (MOSFETs) when operating in the weak inversion region. Furthermore, a block was introduced in order to compensate the gain’s temperature dependence. The results showed that the operating range for the current that will be measured was more than seven decades using BJTs and five decades by using MOSFETs with a high linearity. The circuit version using MOSFETs was able to measure currents as low as 100 fA. The current gain has also good linearity for over five decades. This circuit has a stable behavior for the range of 20 °C to 40 °C, because of the temperature compensation block.

Low Power Photo-Voltaic Harvesting Matrix Based Boost DC–DC Converter with Recycled and Synchro-Recycled Scheme

Photo-voltaic (PV) power harvest can have decent efficiency when dealing with high power. When operating with a DC–DC boost converter during the low-power harvest, its efficiency and output voltage are degraded due to excessive losses in the converter components. The objective of this paper is to present a systematic approach to designing an efficient low-power photo-voltaic harvesting topology with an improved efficiency and output voltage. The proposed topology uses a boost converter with and extra inductor in recycled and synchro-recycled techniques in continuous current mode (CCM). By exploiting the non-linearity of the PV cell, it reduces the power loss and using the current stored in the second inductor, it enhances the output voltage and output power simultaneously. Further, by utilizing the Metal Oxide Silicon Field Effect Transistor’s (MOSFET) body diode as a switch, it maintains a minimum hardware, and introduces a negligible impact on the reliability. The test results of the proposed boost converters show that it achieves a decent power and output voltage. Theoretical and experimental results of the proposed topologies with a tested prototype are presented along with a strategy to maximize power and voltage conversion efficiencies and output voltage.

Development of energy-efficient IBC with IGBT module for photovoltaic applications

Abstract The proposed study is improvised value-engineered modifications for the basic interleaved boost converter (IBC) by including relevant modifications in circuits, which is expected for a better performance in switching with reduction in losses. The newly modified IBC circuit with insulated gate bipolar transistor (IGBT) along with converter has been experimented by simulations and the results are tabulated to modified IBC with metal oxide silicon field effect transistors. Further experimental analysis and validations of the proposed simulation with hardware developed adopting model SKM195GB066D consisting of IGBTs is presented. This study further enhances and summarises the optimum utilisation and the performance of IBC with the proposed IGBT modules that synchronises power diode. Enhancing the simulation outcomes, the hardware is proposed and developed to be tested for a load up to 1.5 kW with the evaluation of key parameters such as efficiency of the converter.

Heisenberg's Uncertainty Principle and the Gate Capacitance in Quantum Metal Oxide Silicon Field Effect Transistor Devices

Heisenberg's Uncertainty Principle and the Gate Capacitance in Quantum Metal Oxide Silicon Field Effect Transistor Devices

Approach for designing and modelling of nanoscale DG MOSFET devices using Kriging metamodelling technique

In this study, the authors focus mainly on the investigation of Kriging interpolation method to elaborate surrogate models of the nanoscale double‐gate metal oxide silicon field effect transistors (DG MOSFET) analogue/RF performance under critical operational conditions. The elaboration of such models is made possible through the generation of computer experiments using ATLAS‐2D simulator, where the numerical simulations or experimental measurements, account for the accurate behaviour of the device including the ageing phenomena, short channel and quantum confinement effects. The validity of the obtained Kriging models is tested by comparing the predicted responses of the device with their numerical counterpart in terms of some statistical criteria namely the sum of relative errors, the mean percentage of absolute errors and the correlation coefficient. It is also shown that the obtained Kriging interpolation models are precise enough to be used as objective functions in the context of a genetic algorithm optimisation with the aim of improving the device analogue/RF performance in terms of transconductance and cut‐off frequency parameters. Therefore, this study may provide more insights regarding the investigation of surrogate modelling tools in the field of deep nanoscale devices especially with the intractable mission of developing physical based models at this scale for nanoelectronic simulators.

Thermal oxidation of silicon in a residual oxygen atmosphere—the RESOX process—for self-limiting growth of thin silicon dioxide films

We describe in detail the growth procedures and properties of thermal silicon dioxide grown in a limited and dilute oxygen atmosphere. Thin thermal oxide films have become increasingly important in recent years due to the continuing down-scaling of ultra large scale integration metal oxide silicon field effect transistors. Such films are also of importance for organic transistors where back-gating is needed. The technique described here is novel and allows self-limited formation of high quality thin oxide films on silicon surfaces. This technique is easy to implement in both research laboratory and industrial settings. Growth conditions and their effects on film growth have been described. Properties of the resulting oxide films, relevant for microelectronic device applications, have also been investigated and reported here. Overall, our findings are that thin, high quality, dense silicon dioxide films of thicknesses up to 100 nm can be easily grown in a depleted oxygen environment at temperatures similar to that used for usual silicon dioxide thermal growth in flowing dry oxygen.

Dopant‐free complementary metal oxide silicon field effect transistors

AbstractAbstractauthoren We present a dopant‐free CMOS technology where n‐ and p‐type semiconductor contacts are realized exclusively based on ultrathin silicon nitrides and metals with appropriate work function. Ellipsometry and FTIR measurements are applied to characterize the thermally grown nitride layers. Unipolar behavior and ohmic contact behavior are accomplished showing that with an appropriate nitride thickness dangling bonds as well as metal‐induced gap states can be suppressed, thus yielding a depinning of the Fermi level. n‐type and –for the first time – p‐type MOSFETs using low‐ and high‐work‐function metals such as aluminum, nickel, or platinum are successfully presented. In contrast to (metal–silicon) Schottky‐barrier MOSFETs, the fabricated devices exhibit on/off ratios larger than .

Recovery and universality in NBTI

The fast recovery behavior in negative bias temperature instability (NBTI) in SiON gate p-type metal–oxide–silicon field effect transistors was investigated. The fast recovery is due to the hole detrapping from the K-center (N3Si, where denotes a dangling bond). The Gaussian function-like hole trap energy level distribution explains the universality in the fast recovery. The results shed light on the NBTI mechanism.

Modeling of subthreshold characteristics of short channel junctionless cylindrical surrounding-gate nanowire metal–oxide–silicon field effect transistors

A subthreshold model of short-channel junctionless field effect transistors with cylindrical surrounding-gate nanowire structure has been proposed. It was based on an approximated solution of two-dimensional Poisson's equation. The derivation of this model was introduced and the accuracy of the proposed models have been verified by comparison with both previous models and the SILVACO Atlas TCAD simulation results, which show good agreement.

Electrical properties of P-MOSFETs on amorphized and regrown (110) SOI film for hybrid orientation technology

A deep amorphization and solid phase epitaxial regrowth (AR) process to convert the initial crystal orientation has been investigated with the aim of co-integrating the (100) and the (110) Si surfaces on a buried oxide. P-channel metal oxide silicon field effect transistors(PMOSFETs) were fabricated on 20-nm-thick Si film silicon-on-insulator(SOI) wafers with and without the AR process. The electrical properties, such as the carrier mobility, transconductance, threshold voltage, and sub-threshold slope, were analyzed by comparing the AR-processed and the reference devices. The experimental results show that the AR process does not alter the original electrical properties of the material. Both (100)- and (110)- oriented Si films could be integrated on a continuous buried oxide.

Deep Trench Filling 기술을 적용한 600 V급 Super Junction Power MOSFET의 최적화 특성에 관한 연구

Power MOSFET(metal oxide silicon field effect transistor) operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. But on-resistance characteristics depending on the increasing breakdown voltage spikes is a problem. So 600 V planar power MOSFET compare to 1/3 low on-resistance characteristics of super junction MOSFET structure. In this paper design to 600 V planar MOSFET and super junction MOSFET, then improvement of comparative analysis breakdown voltage and resistance characteristics. As a result, super junction MOSFET improve on about 40% on-state voltage drop performance than planar MOSFET.

Sub-THz radiation room temperature sensitivity of long-channel silicon field effect transistors

AbstractRoom temperature operating n-MOSFETs (n-type metal-oxide silicon field effect transistors) used for registration of sub-THz (sub-terahertz) radiation in the frequency range ν = 53−145 GHz are considered. n-MOSFETs were manufactured by 1-μm Si CMOS technology applied to epitaxial Si-layers (d ≈15 μm) deposited on thick Si substrates (d = 640 μm). It was shown that for transistors with the channel width to length ratio W/L = 20/3 μm without any special antennas used for radiation input, the noise equivalent power (NEP) for radiation frequency ν ≈76 GHz can reach NEP ∼6×10−10 W/Hz1/2. With estimated frequency dependent antenna effective area Sest for contact wires considered as antennas, the estimated possible noise equivalent power NEPpos for n-MOSFET structures themselves can be from ∼15 to ∼103 times better in the specral range of ν ∼55–78 GHz reaching NEPpos ≈10−12 W/Hz1/2.

Effects of Ion Species on SEB Failure Voltage of Power DMOSFET

This paper presents and explains test results showing the effect of ion species on the single event burnout (SEB) failure voltage using a SEB sensitive engineering power double diffused metal oxide silicon field effect transistor (DMOSFET). The analyses show the determining factor of tested SEB failure voltage is the ion species itself rather than test or beam conditions such as initial beam energy, surface linear energy transfer (LET), ion range, or ionized charge. Also, results from five test facilities and five test setups are compared to determine if there will be differences in test results when different test setups or different heavy ion accelerator facilities were used.

MOSFET on Thin Si Diaphragm as Pressure Sensor

This paper presents original designs of pressure sensor combining thin membrane micro-technology with a simple MOSFET (Metal Oxide Silicon Field Effect Transistor) detection. The proposed microelectronic process (fig. 1) is quite simple and could lead to the development of low pressure sensor. The sensor designs are based on square and cross shaped P-channel MOSFET directly integrated on the diaphragm. Electrical characterization of the FET-sensor shows wide drift of the characteristics in response to mechanical strain on the membrane. The shift importance is shown to depend on the different designs used to fabricate the FET-sensors.

Quantum Mechanical Simulation of Hole Transport in &lt;I&gt;p&lt;/I&gt;-Type Si Schottky Barrier MOSFETs

A full quantum-mechanical simulation of p-type nanowire Schottky barrier metal oxide silicon field effect transistors (SB-MOSFETs) is performed by solving the three-dimensional Schrödinger and Poisson's equations self-consistently. The non-equilibrium Green's function (NEGF) approach is adopted to treat hole transport, especially quantum tunneling through SB. In this work, p-type nanowire SB-MOSFETs are simulated based on the 3-band k.p method, using the k.p parameters that were tuned by benchmarking against the tight-binding method with sp3s* orbitals. The device shows a strong dependence on the transport direction, due to the orientation-sensitive tunneling effective mass and the confinement energy. With regard to the subthreshold slope, the [110] and [111] oriented devices with long channel show better performance, but they are more vulnerable to the short channel effects than the [100] oriented device. The threshold voltage also shows a greater variation in the [110] and [111] oriented devices with the decrease of the channel length.

High-density Nano-scale N-channel Trench-gated MOSFETs Using the Self-aligned Technique

We propose a novel process technology for fabricating a very high density n-channel trench-gate metal oxide silicon field effect transistor (MOSFET) by using an oxide spacer and self-aligned techniques. Due to this nano-scale technology, the cell pitch of the trench-gate MOSFET could be reduced to 3.0 {mu}m, which resulted in an increase in the cell density and in current driving capability. By reducing masks to four layers, a cost-effective process was available. The self-aligned technique also permits a narrow width of the trench gate on the scale of 300 nm. The fabricated device exhibits a specific on-resistance of 1.4 m{Omega}{center_dot}cm{sup 2} for a breakdown voltage of 114.8 V. Moreover, the long-term gate oxide's integrity was improved by adopting corner rounding and hydrogen annealing technologies.