Metal Oxide Semiconductor Structures Research Articles

Analysis of interface trap induced ledge in β-Ga2O3 based MOS structures using UV-assisted capacitance–voltage measurements

A ledge feature in the capacitance–voltage (CV) profiles of Ga2O3 MOS (metal–oxide–semiconductor) capacitors is investigated using UV-assisted CV measurements. A model is presented whereby the capacitance ledge is associated with carrier trapping in deep-level states at the Al2O3/Ga2O3 interface. Following UV assisted emptying of interface traps at a constant bias, a voltage ramp toward flatband results in a CV ledge when the trap recombination current becomes equal to the quasi-static sweep charging current. The ledge continues until all the traps below the corresponding pinned surface potential have been filled. Varying the UV energy varies the ledge voltage range and allows a density of states to be determined as a function of energy. A broad interface state peak with maximum density ∼8 × 1012 cm−2 eV−1 for deep trap energies lying between 2.4 and 4.1 eV below the conduction band (CB) edge is extracted. Using the conductance method, the interface trap density is also found to rise toward the CB edge in the range 0.25–0.45 eV below the CB edge, reaching a maximum density of ∼1 × 1012 cm−2 eV−1. Combining these two techniques, an interface trap distribution is estimated for almost the entirety of the bandgap of Ga2O3. This novel technique probes deep interface states where standard methods fail to quantify interface states reliably.

On the improved RF performance of step field plate LDMOS transistor

This paper presents an analysis of the Step Field Plate Laterally Diffused Metal Oxide Semiconductor (SFP LDMOS) structure for improved high power and RF performance. The proposed structure is cost-effective, CMOS integrable, and has a high power figure of merit (FoM) due to its high off-state breakdown voltage (BVDS,off) and low specific on-resistance (Rsp). Significant improvement in frequency behavior is observed, as demonstrated by the flatter trans-conductance (gm), 12.5x lower gate-to-drain capacitance (Cgd), 2.5x lower gate-to-source capacitance (Cgs), and lower output conductance (gds). Single tone and double tone analyses are performed on an RF PA circuit implemented in TCAD. Results show ∼5 dBm higher output power (Pout), ∼6 dB higher power gain, and 46% higher drain efficiency (η), which are attributed to ∼1.9x lower drain-to-source capacitance (Cds) and ∼15 dBm lower magnitude of third-order intermodulation distortion due to lower third order derivative of drain current (ID). The paper also explains the device physics behind these observations.

Characterization of nitrided SiC(1 [formula omitted] 00) MOS structures by means of electrical measurements and X-ray photoelectron spectroscopy

Interface nitridation in nitric oxide is a standard technique for improving the performance of silicon carbide (SiC) metal-oxide-semiconductor (MOS) devices. In this study, we focused on m-face SiC MOS structures and investigated the impact of nitridation by means of electrical measurements and X-ray photoelectron spectroscopy (XPS). Gate leakage characteristics were measured in a wide temperature range of about −150 – 100 °C, which clarified that nitridation leads to an unwanted increase in the Fowler-Nordheim leakage current. Scanning XPS measurements revealed that the amount of nitrogen incorporated at the m-face MOS interface could reach about 2.3 times higher than the Si-face MOS interface. The incorporation of nitrogen likely reduces the conduction band offset at the SiO2/SiC interface, thereby increasing the gate leakage. This conclusion was further corroborated in an analysis of band alignment based on synchrotron radiation XPS measurements. Therefore, while nitrided m-face SiC MOS devices exhibit superior on-state performances, they have a limitation in terms of reliability.

The effect of deposition temperature on structural, morphological and dielectric properties of Yttria-doped zirconia thin films

The aim of this study was to investigate the effect of deposition temperature on the structural, optical, morphological and dielectric properties of yttria-stabilised zirconia (YSZ) films prepared by sol-gel spin-coating method. X-ray diffraction (XRD) measurements of YSZ films showed that the peaks of the cubic phase were prominent and the peak intensities increased with deposition temperature. The crystallite size, dislocation density and microstrain of the thin films were identified by XRD. It was observed that the crystal size of the YSZ thin films increased from 16 nm to 22 nm with the deposition temperature. The surface roughness of the thin films was found to have changed as revealed by Atomic Force Microscopy (AFM) measurements. The roughness increased from 7.72 nm to 11.92 nm with increasing temperature. The optical transmittance of the YSZ thin films was investigated in the wavelength range 200-900 nm and was found to increase slightly with increasing deposition temperature. Metal-Oxide-Semiconductor (MOS) devices were fabricated from these YSZ materials for dielectric characterization. The dielectric properties of the Ag/YSZ/n-Si MOS structure were investigated. It was found that the capacitance, conductivity and other dielectric parameters of these structures are strongly frequency dependent.

Separate evaluation of interface and oxide hole traps in SiO2/GaN MOS structures with below- and above-gap light excitation

Understanding the traps in metal-oxide-semiconductor (MOS) structures is crucial in the fabrication of MOS transistors with high performance and reliability. In this study, we evaluated the hole traps in SiO2/GaN MOS structures through photo-assisted capacitance-voltage measurements. Below- and above-gap light was used to distinguish between the contributions of fast interface and slow oxide hole traps. While annealing in oxygen is effective in reducing the oxide hole traps, a high density of hole traps exceeding 1012 cm−2eV−1 remains at the interface. Although these traps are donor-type and thus hidden in n-type MOS structures, they could impair the switching performance of GaN MOS transistors.

Annealing‐Free Ohmic Contacts to n‐Type GaN via Hydrogen Plasma‐Assisted Atomic Layer Deposition of Sub‐Nanometer AlOx

AbstractA plasma‐assisted atomic layer deposition (PE‐ALD) process is reported for creating ohmic contacts to n‐type GaN that combines native oxide reduction, near‐surface doping, and encapsulation of GaN in a single processing step, thereby eliminating the need for both wet chemical etching of the native oxide before metallization and thermal annealing after contact formation. Repeated ALD cycling of trimethyl aluminum (TMA) and high‐intensity hydrogen (H2) plasma results in the deposition of a sub‐nanometer‐thin (≈8 Å) AlOx layer via the partial transformation of the GaN surface oxide into AlOx. Hydrogen plasma‐induced nitrogen vacancies in the near‐surface region of GaN serve as shallow donors, promoting efficient out‐of‐plane electrical transport. Subsequent metallization with a Ti/Al/Ti/Au stack results in low contact resistance, ohmic behavior, and smooth morphology without requiring annealing. This electrical contracting approach thus meets the thermal budget requirements for Si‐based complementary metal–oxide–semiconductor structures and can facilitate the design and fabrication of advanced GaN‐on‐Si heterodevices.

Extension of Surface Charge Density Studies of Metal Oxide Semiconductor (MOS) Structure to Polarization Studies of Metal Ferroelectric Metal (MFM) Structure in Bulk Form: Experimental and Simulation of Polarization Data

Ba(NdxTi(1-2x)Nbx)O3 and (Na0.5Bi0.5)(NdyTi1-2yNby)O3 relaxor ferroelectric materials were prepared through solid state sintering route. The polarization as a function of electric field (PE loops) were measured with Radiant technologies PE loop tracer. In the present studies we have extended the surface charge density studies of metal oxide semiconductor (MOS) structure to the polarization studies of metal ferroelectric and metal (MFM) structure in bulk form by combining it with the modified Glazounov and Arrhenius equations. The simulation is in good agreement the experimental data. In the case of Ba(NdxTi(1-2x)Nbx)O3 ceramics the value of dipole moment (p) are 2.24x10−26 C.m, 1.80x10−26 C.m, 2.23x10−26 C.m & 2.21x 10−26 C.m for x = 0.025, 0.05, 0.1 & 0.2, respectively. The values of surface potential (Ψp) are 466 meV, 503 meV, 552 meV & 505 meV for x = 0.025, 0.05, 0.1 & 0.2, respectively.

Plasma-assisted deposition and characterization of Al2O3 dielectric layers on (001) β -Ga2O3

In this work, we have investigated plasma-assisted deposition of Al2O3 on HVPE (001) β-Ga2O3 and evaluated the dielectric quality from electrical measurements on fabricated metal-oxide-semiconductor (MOS) capacitors. The interface structure and crystallinity of the films were investigated as a function of the growth temperature. The dielectric/semiconductor interfaces were found to have reverse breakdown electric fields up to 5.3 MV/cm in the β-Ga2O3, with relatively low hysteresis in capacitance–voltage and low leakage current. We determined a negative fixed interface charge density at the interface from analysis of thickness-dependent capacitance voltage data. This study shows the advantage of using plasma-assisted deposition to achieve high breakdown strength Al2O3/β-Ga2O3 MOS structures for device application purposes.

Infrared Surface Plasmons Open a Hole Tunneling Channel in Metal–Oxide–Semiconductor Structures

Infrared Surface Plasmons Open a Hole Tunneling Channel in Metal–Oxide–Semiconductor Structures

Simulation of Total Ionizing Dose Effects Technique for CMOS Inverter Circuit.

The total ionizing dose (TID) effect significantly impacts the electrical parameters of fully depleted silicon on insulator (FDSOI) devices and even invalidates the on-off function of devices. At present, most of the irradiation research on the circuit level is focused on the single event effect, and there is very little research on the total ionizing dose effect. Therefore, this study mainly analyzes the influence of TID effects on a CMOS inverter circuit based on 22 nm FDSOI transistors. First, we constructed and calibrated an N-type FDSOI metal-oxide semiconductor (NMOS) structure and P-type FDSOI metal-oxide semiconductor (PMOS) structure. The transfer characteristics and trapped charge distribution of these devices were studied under different irradiation doses. Next, we studied the TID effect on an inverter circuit composed of these two MOS transistors. The simulation results show that when the radiation dose was 400 krad (Si), the logic threshold drift of the inverter was approximately 0.052 V. These results help further investigate the impact on integrated circuits in an irradiation environment.

LPT and SLPT Measurement Methods of Flat-Band Voltage (VFB) in MOS Devices

The photoelectric techniques are often used for the measurements of metal oxide semiconductor (MOS) structure parameters. These methods, which consist in illuminating the MOS structure with a semitransparent metal gate by a UV light beam, are often competitive for typical electric measurements. The results obtained by different photoelectric methods are, in many cases, more accurate and reproducible than the results of other measurements. The flat-band voltage VFB is an important parameter of any MOS structure since its value influences the threshold voltage VT , which decides for example about power consumption of MOS transistors. One of the methods to measure the VFB value is the electric method of C(V) characteristic. This method involves certain calculations and requires the knowledge about parameters of the investigated sample. The accuracy of this method is rarely better than ±100 mV (for higher doping of the substrates the accuracy is worse). The other method of VFB value determination, outlined in this article, is the photoelectric light pulse technique (LPT) method. This method based on the idea proposed by Yun is currently being optimized and verified experimentally.

High-speed polarization-independent plasmonic modulator on a silicon waveguide.

The electrical bandwidth of an electro-optic modulator plays a vital role in determining the throughput of an optical communications link. We propose a broadband plasmonic electro-optic modulator operating at telecommunications wavelengths (λ0 ∼ 1550 nm), based on free carrier dispersion in indium tin oxide (ITO). The ITO is driven through its epsilon-near-zero point within the accumulation layers of metal-oxide-semiconductor (MOS) structures. The MOS structures are integrated into a pair of coupled metal-insulator-metal (MIM) waveguides aligned on a planarized silicon waveguide. The coupled MIM waveguides support symmetric and asymmetric plasmonic supermodes, excited adiabatically using mode transformation tapers, by the fundamental TM0 and TE0 modes of the underlying silicon waveguide, respectively, such that the modulator can operate in either mode as selected by the input polarisation to the silicon waveguide. The modulator has an active section 1.5 to 2 µm long, enabling the modulator to operate as a lumped element to bandwidths exceeding 200 GHz (3 dB electrical, RC-limited). The modulators produce an extinction ratio in the range of 3.5 to 6 dB, and an insertion loss in the range of 4 to 7.5 dB including input/output mode conversion losses. The AC drive voltage is ±1.75 V. The devices comprise only inorganic materials and are realisable using standard deposition, etching and nanolithography techniques.

Tunable Hybrid Plasmonic Semiconductor Laser Based on Loss Perturbation

We propose a tunable plasmonic semiconductor laser that exploits loss perturbation as a tuning mechanism. A metal oxide semiconductor (MOS) capacitive structure is added on top of an edge-emitting Fabry-Perot (FP) diode laser, such that a hybrid plasmonic TM mode that overlaps partly with the MOS capacitor and the semiconductor gain region is supported as the lasing mode. We also propose the use of a layer of conductive oxide, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e.g</i> ., indium tin oxide (ITO), as the semiconductor of the MOS structure, because the epsilon near zero (ENZ) condition can be attained therein under accumulation, thereby producing a very large change in the effective index of the hybrid plasmonic TM mode. The change in the imaginary part of the effective index is used to tune the lasing wavelength - exploiting loss perturbation to achieve laser tuning is paradigm-shifting. The laser proposed operates at telecom wavelengths, requiring an electrical forward bias to pump the active layer, and a gate voltage to drive the MOS tuning capacitor. Simulations yield a tuning range of over 7 nm in the O-band for a 100 μm long FP laser cavity.

Low temperature atomic hydrogen annealing of InGaAs MOSFETs

Recent work showing a strong quality improvement of the Si/SiO2 material system by low temperature atomic hydrogen annealing (AHA), and the fact that III–V semiconductors outperform Si in many applications makes the investigation of AHA on III–V/high-k interfaces to a very interesting topic. In this work, the potential of AHA as a low temperature annealing treatment of InGaAs metal–oxide–semiconductor field-effect transistors is presented and compared to conventional annealing in a rapid thermal process (RTP) system using forming gas. It is found that post metal annealing in atomic hydrogen greatly enhances the quality of the metal–oxide–semiconductor structure in terms of effective mobility, minimum subthreshold swing, and reliability. The device performance is comparable to RTP annealing but can be performed at a lower temperature, which opens up for integration of more temperature-sensitive materials in the device stack.

Poole-Frenkel (PF)-MOS: A Proposal for the Ultimate Scale of an MOS Transistor.

This work reports, for the first time, the phenomenon of lateral Poole-Frenkel current conduction along the dielectric/Si interface of a silicon nanowire metal-oxide semiconductor (MOS) transistor. This discovery has a great impact on the study of device characteristic modeling and device reliability, leading to a new kind of electronic device with a distinct operation mechanism for replacing the existing MOS transistor structure. By measuring the current-voltage characteristics of silicon nanowire MOS transistors with different nanowire widths and at elevated temperatures up to 450 K, we found that the current level in the conventional ohmic region of MOS transistors, especially for the transistors with a nanowire width of 10 nm, was significantly enhanced and the characteristics are no longer linear or in an ohmic relationship. The enhancement strongly depended on the applied drain voltage and strictly followed the Poole-Frenkel emission characteristics. Based on this discovery, we proposed a new type of MOS device: a Poole-Frenkel emission MOS transistor, or PF-MOS. The PF-MOS uses the high defect state Si/dielectric interface layer as the conduction channel and is expected to possess several unique features that have never been reported. PF-MOS could be considered as the ultimate MOS structure from a technological point of view. In particular, it eliminates the requirement of a subnanometer gate dielectric equivalent oxide thickness (EOT) and eradicates the server mobility degradation issue in the sub-decananometer nanowires.

Tunable plasmonics on epsilon-near-zero materials: the case for a quantum carrier model.

The carrier density profile in metal-oxide-semiconductor (MOS) capacitors is computed under gating using two classical models - conventional drift-diffusion (CDD) and density-gradient (DG) - and a self-consistent Schrödinger-Poisson (SP) quantum model. Once calibrated the DG model approximates well the SP model while being computationally more efficient. The carrier profiles are used in optical mode computations to determine the gated optical response of surface plasmons supported by waveguides incorporating MOS structures. Indium tin oxide (ITO) is used as the semiconductor in the MOS structures, as the real part of its optical permittivity can be driven through zero to become negative under accumulation, enabling epsilon-near-zero (ENZ) effects. Under accumulation the predictions made by the CDD and SP models differ considerably, in that the former predicts one ENZ point but the latter predicts two. Consequently, the CDD model significantly underestimates perturbations in n e f f of surface plasmons (by ∼4×) and yields incorrect details in surface plasmon fields near ENZ points. The discrepancy is large enough to invalidate the CDD model in MOS structures on ENZ materials under accumulation, strongly motivating a quantum carrier model in this regime.

Mobility degradation under a high effective normal field in an inversion layer of 4H-SiC (0001) metal–oxide–semiconductor structures annealed in POCl3

Mobility degradation under a high effective normal field (1 MV cm−1 < E eff < 2 MV cm−1) in an inversion layer of 4H-silicon carbide (SiC) (0001) metal–oxide–semiconductor field-effect transistors (MOSFETs) annealed in POCl3 is investigated by applying a negative body bias (0 V ≥ V BS ≥ −40 V). The effective channel mobility (μ eff) is proportional to E eff −2.3–−2.2 in the range 1 MV cm−1 ≤ E eff. On the basis of the obtained results, the authors propose that the mobility degradation in the high-E eff region is caused by strong surface roughness scattering in SiC MOSFETs with a very low interface state density.

Detection of defect levels in vicinity of Al2O3/p-type GaN interface using sub-bandgap-light-assisted capacitance–voltage method

Defect levels in the vicinity of the Al2O3/p-type GaN interface were characterized using a sub-bandgap-light-assisted capacitance–voltage (C–V) method. For metal–oxide–semiconductor (MOS) diodes prepared using p-type GaN (p-GaN) and Al2O3 formed by atomic layer deposition, the C–V curves measured in the dark showed capacitance saturation at a negative bias and a large negative voltage shift compared with ideal curves, which implied the effects of donor-like gap states in the vicinity of the Al2O3/p-GaN interface. Upon illumination with monochromated sub-bandgap light with photon energies higher than 2.0 eV under a large positive bias, the subsequently measured C–V curves showed three plateaus. The plateau under the positive bias voltage due to the surface inversion appeared despite the sub-bandgap illumination, which did not appear at 1.8 eV light illumination, indicating the existence of midgap defect levels. Moreover, the other plateaus were attributed to defect levels at 0.60 and 0.7–0.8 eV above the valence band maximum. For a sample whose surface was prepared by photo-electrochemical (PEC) etching to a depth of 16.5 nm, the C–V curve measured in the dark showed a reduced voltage shift compared with the unetched sample. Furthermore, sub-bandgap-light-assisted C–V curves of the sample with PEC etching showed no plateau at a positive bias, which indicated the reduction in the density of the midgap defect states. Possible origins of the detected defect levels are discussed. The obtained results showed that the interface control can improve the properties of p-GaN MOS structures.

Electrically tuning near-field heat flux using metal–oxide–semiconductor structure considering gradient dielectric function distribution

We build a model to determine the dependency of near-field heat flux on bias voltage using the metal–oxide–semiconductor structures considering gradient distribution of dielectric function. Quantitative dependency of near-field heat flux exchanged by two biased metal–oxide–semiconductor structures on bias voltage is established. The distribution of carrier density and the resultant dielectric function in the semiconductor layer caused by the bias are determined. The corresponding near-field heat flux is calculated using an effective multilayer model. Significant tuning performance is demonstrated, which is due to the increase or decrease in high-frequency surface polariton states induced by the injection or extraction of major carriers. This work deepens the understanding of electrical control of near-field heat transfer with metal–oxide–semiconductor structures, promising for nanoscale thermal management devices and thermal circuits.

Thermal characterization and stress analysis of Ho2O3 thin film on 4H–SiC substrate

The performance of a metal oxide semiconductor during operation could be hindered significantly due to thermodynamic instability and mismatch between the gate oxide layer and the substrate. Owing to variation in temperature during thermal applications, the thin film layers and substrates in complementary metal oxide semiconductor (CMOS) structures are subjected to high thermal stresses, which can result in large deformation and failure. In this study, the distribution of heat and thermal stress between the Ho2O3 thin film and the SiC substrate has been simulated numerically with finite element modelling and analysis software (ANSYS). This is necessary to emulate the thermal behaviour of the structure under different thermal loadings, and for each temperature loading, the effects of thermal stress and deformation on the structure were also evaluated. Based on the results of the simulation, an optimum temperature was suggested. The thermal stability and characteristics of the thin film layer/SiC structure were evaluated and validated for better electrical performance.