Metal Oxide Semiconductor Structures Research Articles

Accumulation and Erase of Radiation-Induced Charge in MOS Structures

It is shown that when a MOS (metal–oxide–semiconductor) structure is simultaneously exposed to radiation and high-field injection of electrons, part of the radiation-induced positive charge can be erased when interacting with injected electrons, and the density of surface states can increase. These phenomena must be taken into account when operating MOS radiation sensors in high-field charge injection modes. High-field injection modes used for post-radiation erase of positive charge in MOS sensors are analyzed. It has been established that to annihilate one hole (radiation-induced positive charge), it is necessary to inject (0.5–2) × 104 electrons into the gate dielectric; the magnitude of the electric field has almost no effect on the process of erasing the radiation-induced charge.

MOS-structured MoS2/GaN Schottky barrier diodes with high on/off current ratio and low threshold voltage

GaN Schottky barrier diodes (SBDs) have been investigated for a variety of power applications. However, the problems of low on/off current ratio and high threshold voltage caused by the difficult high-quality doping restrict its utilization in power devices. In this work, quasi-vertical MoS2/GaN SBDs with Metal-Oxide-Semiconductor (MOS) structure have been proposed. The MOS structure is formed by the part of anode (Ni/Au) over the Al2O3, Al2O3, and monolayer MoS2. Monolayer MoS2 exhibits n-type doping and p-type doping under forward bias and reverse bias, respectively, which realizes an adjustment in the Fermi level of the monolayer MoS2, resulting in a change in the resistance of the SBDs. The as-prepared SBDs present a high on/off current ratio of 2.40 × 1011, a low threshold voltage of 0.55 V at 1 A/cm2, and a low reverse leakage current of 2.50 × 10−10 A/cm2 at −1 V. This work shows that the MOS-structured MoS2/GaN SBDs are promising for next-generation power electronics.

Impact of Oxide Charges on The Minority Carrier Response in MOS(p) Devices With Al2O3/SiO2 Gate Stacks under Strong Inversion Condition

Admittance measurement, including capacitance and conductance, is very useful to analyze the electrical characteristics of metal-oxide-semiconductor (MOS) systems. These techniques offer insights into various device properties, including interface trap density and minority carrier lifetime in the substrate. It is essential to note that, apart from the gate area, the oxide region beyond the device could significantly influence measurement results [1]-[2]. In this work, a compact model proposed in [3] was used to clarify an unusual minority carrier response time observed in experimental data. The results proved the heightened sensitivity of device alternating current (AC) characteristics to oxide charges in the outer region. Additionally, the dependencies of oxide thickness and quality on the transition frequency (ωm) of devices were explored.The MOS (Al/AlOx/SiO2/p-Si) structure illustrated in Fig. 1 was employed in this study. Aluminum oxide region is under the gate electrode, while silicon oxide (SiO2) covers the entire wafer. Table 1 summarizes samples (S1 to S5) with consistent aluminum oxide thickness but diverse SiO2 thickness. Fig 2. shows the process flow and the anodic oxidation (ANO) system. By tilting the wafer at a specific angle during ANO, a high-quality SiO2 layer with different thicknesses on a single wafer could be obtained. Fig 3(a) to (d) illustrate the capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics of devices with varying SiO2 thicknesses. All devices exhibit low-frequency capacitance characteristics in strong inversion regions with thickness-dependent minority carrier response, particularly at 10kHz. Additionally, devices show different thicknesses depending on G-V characteristics at 1MHz and 10kHz. Fig 4(a) and (b) illustrate the Cinv/Cox ratio for varied oxide thicknesses and Gm/ω characteristics under strong inversion bias (VG = +3V). Gm means the measurement conductance. Following established research [3], peak Gm/ω magnitudes would occur at ωm. Table 2 reveals microsecond-range response times (τR) at ωm, considerably faster than conventional silicon minority carrier lifetimes (usually 1 ms to 100 ms). Moreover, decreasing oxide thickness shifts the ωm toward lower values.To explain this observed phenomenon, the environment outside the devices should be taken into consideration. Fig 5(a) and (b) show the schematic diagram and AC signal model proposed in [1] and [2]. Oxide charges in the outer region would deplete majority carriers and invert the p-type silicon surface to an n-type inversion layer. As a result, the lateral depletion region (Cd, out) and conductive channel (Rs) are formed outside the device, which are functions of substrate doping concentration and the effective oxide charges. The detailed model derivation is discussed in [2]. For this reason, an AC signal applied on the gate would extend outside the device for about a millimeter to a micrometer, affecting measuring results. Based on the model, the effective charges in the SiO2 could be extracted by measuring results. The thicker oxide has more oxide charges, as shown in Fig 6(a). Fig 6(b) and (c) show the modeling results of the Cinv/Cox ratio versus different oxide thicknesses and the Gm/ω-ω plot, which are very close to the experimental results. By simplifying the conductance formula (Gm), Gm reveals an inverse proportional to lateral effective conductance (GLeff) at low frequency (e.g., 10 kHz) and a direct proportional at high frequency (e.g., 1 MHz). Thicker SiO2 devices possess more oxide charges, leading to a greater lateral coupling effect, resulting in a greater GLeff compared to thinner devices. This elucidates the observed variations in Gm-V characteristics at 1 MHz and 10 kHz. Figures 7(a) and (b) display TCAD-simulated C-V and ωm for devices with varying oxide charge densities, confirming that minor changes in oxide charges result in noticeable differences in minority carrier responses in the strong inversion region. Fig 8(a) and (b) show the TCAD simulated results for devices with low doping substrate. For low doping substrates, oxide charges play a much more important role under AC operation.In summary, the study established a correlation between oxide charge densities and thicknesses. The origin of the faster minority carrier response and the peak shift in Gm/ω- ω plot were thoroughly explained and validated by TCAD simulation. Oxide charges were found to play a crucial role, especially in low-doping substrates, offering insights for advanced IC fabrication.[1] E. H. Nicollian and A. Goetzberger, IEEE Transactions on Electron Devices, vol. 12, no. 3, pp. 108-117, 1965.[2] K. C. Chen, K. W. Lin, S. W. Huang, J. Y. Lin, and J. G. Hwu, IEEE Journal of the Electron Devices Society, vol. 10, pp. 960-969, 2022.[3] S. Monaghan et al., IEEE Transactions on Electron Devices, vol. 61, no. 12, pp. 4176-4185, 2014. Figure 1

Enhancing the radiation hardness of vertical 4H–SiC detectors by the metal-oxide-semiconductor structure

In this work, 4H–SiC α-particle detectors with metal/semiconductor (MS) and metal/oxide/semiconductor (MOS) structures have been fabricated. The effects of introducing a SiO2 dielectric layer to form a MOS structure on the electrical properties, the performances, and the radiation hardness of the detectors have been evaluated systematically by comparing those with the MS structure. It is found that the reverse leakage current and the signal-to-noise ratio of α-particle detectors at high voltages can be improved by the MOS structure. Furthermore, the MOS structure exhibits much higher radiation hardness, as the energy resolution degradation of α particle detectors with MOS and MS structures after the γ irradiation is 0.59% and 2.87%, respectively. This work may provide a way to enhance the radiation hardness of 4H–SiC α-particle detectors.

Experimental demonstration of plasmon–plasmon scattering paves the way for electromagnetic wave-based digital logic concept

We report the experimental demonstration of plasmon–plasmon scattering at room temperature in the inversion layer of a patterned metal–oxide–semiconductor structure. This fundamental result paves the way for the development of plasmon–plasmon scattering logic, a revolutionary digital logic concept based on the generation, propagation, and manipulation of plasmons in an electron fluid, which was previously theoretically projected to exhibit femtojoule power dissipations and femtosecond switching speeds, while not demanding expensive nanometer-scale silicon (Si) technology fabrication processes for its implementation.

Analysis of interface trap induced ledge in β-Ga2O3 based MOS structures using UV-assisted capacitance–voltage measurements

A ledge feature in the capacitance–voltage (CV) profiles of Ga2O3 MOS (metal–oxide–semiconductor) capacitors is investigated using UV-assisted CV measurements. A model is presented whereby the capacitance ledge is associated with carrier trapping in deep-level states at the Al2O3/Ga2O3 interface. Following UV assisted emptying of interface traps at a constant bias, a voltage ramp toward flatband results in a CV ledge when the trap recombination current becomes equal to the quasi-static sweep charging current. The ledge continues until all the traps below the corresponding pinned surface potential have been filled. Varying the UV energy varies the ledge voltage range and allows a density of states to be determined as a function of energy. A broad interface state peak with maximum density ∼8 × 1012 cm−2 eV−1 for deep trap energies lying between 2.4 and 4.1 eV below the conduction band (CB) edge is extracted. Using the conductance method, the interface trap density is also found to rise toward the CB edge in the range 0.25–0.45 eV below the CB edge, reaching a maximum density of ∼1 × 1012 cm−2 eV−1. Combining these two techniques, an interface trap distribution is estimated for almost the entirety of the bandgap of Ga2O3. This novel technique probes deep interface states where standard methods fail to quantify interface states reliably.

On the improved RF performance of step field plate LDMOS transistor

This paper presents an analysis of the Step Field Plate Laterally Diffused Metal Oxide Semiconductor (SFP LDMOS) structure for improved high power and RF performance. The proposed structure is cost-effective, CMOS integrable, and has a high power figure of merit (FoM) due to its high off-state breakdown voltage (BVDS,off) and low specific on-resistance (Rsp). Significant improvement in frequency behavior is observed, as demonstrated by the flatter trans-conductance (gm), 12.5x lower gate-to-drain capacitance (Cgd), 2.5x lower gate-to-source capacitance (Cgs), and lower output conductance (gds). Single tone and double tone analyses are performed on an RF PA circuit implemented in TCAD. Results show ∼5 dBm higher output power (Pout), ∼6 dB higher power gain, and 46% higher drain efficiency (η), which are attributed to ∼1.9x lower drain-to-source capacitance (Cds) and ∼15 dBm lower magnitude of third-order intermodulation distortion due to lower third order derivative of drain current (ID). The paper also explains the device physics behind these observations.

Characterization of nitrided SiC(1 [formula omitted] 00) MOS structures by means of electrical measurements and X-ray photoelectron spectroscopy

Interface nitridation in nitric oxide is a standard technique for improving the performance of silicon carbide (SiC) metal-oxide-semiconductor (MOS) devices. In this study, we focused on m-face SiC MOS structures and investigated the impact of nitridation by means of electrical measurements and X-ray photoelectron spectroscopy (XPS). Gate leakage characteristics were measured in a wide temperature range of about −150 – 100 °C, which clarified that nitridation leads to an unwanted increase in the Fowler-Nordheim leakage current. Scanning XPS measurements revealed that the amount of nitrogen incorporated at the m-face MOS interface could reach about 2.3 times higher than the Si-face MOS interface. The incorporation of nitrogen likely reduces the conduction band offset at the SiO2/SiC interface, thereby increasing the gate leakage. This conclusion was further corroborated in an analysis of band alignment based on synchrotron radiation XPS measurements. Therefore, while nitrided m-face SiC MOS devices exhibit superior on-state performances, they have a limitation in terms of reliability.

The Effect of Deposition Temperature on Structural, Morphological, and Dielectric Properties of Yttria-Doped Zirconia Thin Films

The aim of this study was to investigate the effect of deposition temperature on the structural, optical, morphological, and dielectric properties of yttria-stabilised zirconia (YSZ) films prepared by sol-gel spin-coating method. X-ray diffraction (XRD) measurements of YSZ films showed that the peaks of the cubic phase were prominent and the peak intensities increased with deposition temperature. The crystallite size, dislocation density, and microstrain of the thin films were identified by XRD. It was observed that the crystal size of the YSZ thin films increased from 16 nm to 22 nm with the deposition temperature. The surface roughness of the thin films was found to have changed as revealed by Atomic Force Microscopy (AFM) measurements. The roughness increased from 7.72 nm to 11.92 nm with increasing temperature. The optical transmittance of the YSZ thin films was investigated in the wavelength range 200-900 nm and was found to increase slightly with increasing deposition temperature. Metal-Oxide-Semiconductor (MOS) devices were fabricated from these YSZ materials for dielectric characterization. The dielectric properties of the Ag/YSZ/n-Si MOS structure were investigated. It was found that the capacitance, conductivity and other dielectric parameters of these structures are strongly frequency dependent.

Plasmonic optoelectronic devices and metasurfaces

We report recent progress on optoelectronic devices and metasurfaces involving surface plasmons, enabled by metal-oxide-semiconductor (MOS) structures on Si and on epsilon-near-zero materials. We discuss electrically tuneable metasurfaces, high-speed electro-absorption modulators, and reflection modulators. Hot carriers created by the absorption of plasmons in metallic nanostructures on MOS structures are also discussed as they lead to novel device physics that open the door to new device concepts.

Separate evaluation of interface and oxide hole traps in SiO2/GaN MOS structures with below- and above-gap light excitation

Understanding the traps in metal-oxide-semiconductor (MOS) structures is crucial in the fabrication of MOS transistors with high performance and reliability. In this study, we evaluated the hole traps in SiO2/GaN MOS structures through photo-assisted capacitance-voltage measurements. Below- and above-gap light was used to distinguish between the contributions of fast interface and slow oxide hole traps. While annealing in oxygen is effective in reducing the oxide hole traps, a high density of hole traps exceeding 1012 cm−2eV−1 remains at the interface. Although these traps are donor-type and thus hidden in n-type MOS structures, they could impair the switching performance of GaN MOS transistors.

Annealing‐Free Ohmic Contacts to n‐Type GaN via Hydrogen Plasma‐Assisted Atomic Layer Deposition of Sub‐Nanometer AlOx

AbstractA plasma‐assisted atomic layer deposition (PE‐ALD) process is reported for creating ohmic contacts to n‐type GaN that combines native oxide reduction, near‐surface doping, and encapsulation of GaN in a single processing step, thereby eliminating the need for both wet chemical etching of the native oxide before metallization and thermal annealing after contact formation. Repeated ALD cycling of trimethyl aluminum (TMA) and high‐intensity hydrogen (H2) plasma results in the deposition of a sub‐nanometer‐thin (≈8 Å) AlOx layer via the partial transformation of the GaN surface oxide into AlOx. Hydrogen plasma‐induced nitrogen vacancies in the near‐surface region of GaN serve as shallow donors, promoting efficient out‐of‐plane electrical transport. Subsequent metallization with a Ti/Al/Ti/Au stack results in low contact resistance, ohmic behavior, and smooth morphology without requiring annealing. This electrical contracting approach thus meets the thermal budget requirements for Si‐based complementary metal–oxide–semiconductor structures and can facilitate the design and fabrication of advanced GaN‐on‐Si heterodevices.

Extension of Surface Charge Density Studies of Metal Oxide Semiconductor (MOS) Structure to Polarization Studies of Metal Ferroelectric Metal (MFM) Structure in Bulk Form: Experimental and Simulation of Polarization Data

Ba(NdxTi(1-2x)Nbx)O3 and (Na0.5Bi0.5)(NdyTi1-2yNby)O3 relaxor ferroelectric materials were prepared through solid state sintering route. The polarization as a function of electric field (PE loops) were measured with Radiant technologies PE loop tracer. In the present studies we have extended the surface charge density studies of metal oxide semiconductor (MOS) structure to the polarization studies of metal ferroelectric and metal (MFM) structure in bulk form by combining it with the modified Glazounov and Arrhenius equations. The simulation is in good agreement the experimental data. In the case of Ba(NdxTi(1-2x)Nbx)O3 ceramics the value of dipole moment (p) are 2.24x10−26 C.m, 1.80x10−26 C.m, 2.23x10−26 C.m & 2.21x 10−26 C.m for x = 0.025, 0.05, 0.1 & 0.2, respectively. The values of surface potential (Ψp) are 466 meV, 503 meV, 552 meV & 505 meV for x = 0.025, 0.05, 0.1 & 0.2, respectively.

Plasma-assisted deposition and characterization of Al2O3 dielectric layers on (001) β -Ga2O3

In this work, we have investigated plasma-assisted deposition of Al2O3 on HVPE (001) β-Ga2O3 and evaluated the dielectric quality from electrical measurements on fabricated metal-oxide-semiconductor (MOS) capacitors. The interface structure and crystallinity of the films were investigated as a function of the growth temperature. The dielectric/semiconductor interfaces were found to have reverse breakdown electric fields up to 5.3 MV/cm in the β-Ga2O3, with relatively low hysteresis in capacitance–voltage and low leakage current. We determined a negative fixed interface charge density at the interface from analysis of thickness-dependent capacitance voltage data. This study shows the advantage of using plasma-assisted deposition to achieve high breakdown strength Al2O3/β-Ga2O3 MOS structures for device application purposes.

Infrared Surface Plasmons Open a Hole Tunneling Channel in Metal–Oxide–Semiconductor Structures

Infrared Surface Plasmons Open a Hole Tunneling Channel in Metal–Oxide–Semiconductor Structures

Simulation of Total Ionizing Dose Effects Technique for CMOS Inverter Circuit.

The total ionizing dose (TID) effect significantly impacts the electrical parameters of fully depleted silicon on insulator (FDSOI) devices and even invalidates the on-off function of devices. At present, most of the irradiation research on the circuit level is focused on the single event effect, and there is very little research on the total ionizing dose effect. Therefore, this study mainly analyzes the influence of TID effects on a CMOS inverter circuit based on 22 nm FDSOI transistors. First, we constructed and calibrated an N-type FDSOI metal-oxide semiconductor (NMOS) structure and P-type FDSOI metal-oxide semiconductor (PMOS) structure. The transfer characteristics and trapped charge distribution of these devices were studied under different irradiation doses. Next, we studied the TID effect on an inverter circuit composed of these two MOS transistors. The simulation results show that when the radiation dose was 400 krad (Si), the logic threshold drift of the inverter was approximately 0.052 V. These results help further investigate the impact on integrated circuits in an irradiation environment.

High-speed polarization-independent plasmonic modulator on a silicon waveguide.

The electrical bandwidth of an electro-optic modulator plays a vital role in determining the throughput of an optical communications link. We propose a broadband plasmonic electro-optic modulator operating at telecommunications wavelengths (λ0 ∼ 1550 nm), based on free carrier dispersion in indium tin oxide (ITO). The ITO is driven through its epsilon-near-zero point within the accumulation layers of metal-oxide-semiconductor (MOS) structures. The MOS structures are integrated into a pair of coupled metal-insulator-metal (MIM) waveguides aligned on a planarized silicon waveguide. The coupled MIM waveguides support symmetric and asymmetric plasmonic supermodes, excited adiabatically using mode transformation tapers, by the fundamental TM0 and TE0 modes of the underlying silicon waveguide, respectively, such that the modulator can operate in either mode as selected by the input polarisation to the silicon waveguide. The modulator has an active section 1.5 to 2 µm long, enabling the modulator to operate as a lumped element to bandwidths exceeding 200 GHz (3 dB electrical, RC-limited). The modulators produce an extinction ratio in the range of 3.5 to 6 dB, and an insertion loss in the range of 4 to 7.5 dB including input/output mode conversion losses. The AC drive voltage is ±1.75 V. The devices comprise only inorganic materials and are realisable using standard deposition, etching and nanolithography techniques.

Tunable Hybrid Plasmonic Semiconductor Laser Based on Loss Perturbation

We propose a tunable plasmonic semiconductor laser that exploits loss perturbation as a tuning mechanism. A metal oxide semiconductor (MOS) capacitive structure is added on top of an edge-emitting Fabry-Perot (FP) diode laser, such that a hybrid plasmonic TM mode that overlaps partly with the MOS capacitor and the semiconductor gain region is supported as the lasing mode. We also propose the use of a layer of conductive oxide, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e.g</i> ., indium tin oxide (ITO), as the semiconductor of the MOS structure, because the epsilon near zero (ENZ) condition can be attained therein under accumulation, thereby producing a very large change in the effective index of the hybrid plasmonic TM mode. The change in the imaginary part of the effective index is used to tune the lasing wavelength - exploiting loss perturbation to achieve laser tuning is paradigm-shifting. The laser proposed operates at telecom wavelengths, requiring an electrical forward bias to pump the active layer, and a gate voltage to drive the MOS tuning capacitor. Simulations yield a tuning range of over 7 nm in the O-band for a 100 μm long FP laser cavity.

Low temperature atomic hydrogen annealing of InGaAs MOSFETs

Recent work showing a strong quality improvement of the Si/SiO2 material system by low temperature atomic hydrogen annealing (AHA), and the fact that III–V semiconductors outperform Si in many applications makes the investigation of AHA on III–V/high-k interfaces to a very interesting topic. In this work, the potential of AHA as a low temperature annealing treatment of InGaAs metal–oxide–semiconductor field-effect transistors is presented and compared to conventional annealing in a rapid thermal process (RTP) system using forming gas. It is found that post metal annealing in atomic hydrogen greatly enhances the quality of the metal–oxide–semiconductor structure in terms of effective mobility, minimum subthreshold swing, and reliability. The device performance is comparable to RTP annealing but can be performed at a lower temperature, which opens up for integration of more temperature-sensitive materials in the device stack.

Poole-Frenkel (PF)-MOS: A Proposal for the Ultimate Scale of an MOS Transistor.

This work reports, for the first time, the phenomenon of lateral Poole-Frenkel current conduction along the dielectric/Si interface of a silicon nanowire metal-oxide semiconductor (MOS) transistor. This discovery has a great impact on the study of device characteristic modeling and device reliability, leading to a new kind of electronic device with a distinct operation mechanism for replacing the existing MOS transistor structure. By measuring the current-voltage characteristics of silicon nanowire MOS transistors with different nanowire widths and at elevated temperatures up to 450 K, we found that the current level in the conventional ohmic region of MOS transistors, especially for the transistors with a nanowire width of 10 nm, was significantly enhanced and the characteristics are no longer linear or in an ohmic relationship. The enhancement strongly depended on the applied drain voltage and strictly followed the Poole-Frenkel emission characteristics. Based on this discovery, we proposed a new type of MOS device: a Poole-Frenkel emission MOS transistor, or PF-MOS. The PF-MOS uses the high defect state Si/dielectric interface layer as the conduction channel and is expected to possess several unique features that have never been reported. PF-MOS could be considered as the ultimate MOS structure from a technological point of view. In particular, it eliminates the requirement of a subnanometer gate dielectric equivalent oxide thickness (EOT) and eradicates the server mobility degradation issue in the sub-decananometer nanowires.