Metal Oxide Semiconductor Field Effect Research Articles

The heat dissipation by the multi-needle electrode structure ionic wind generator

Ionic wind generated by atmospheric pressure discharge can be used for propulsion, heat dissipation, food drying, which shows the unique advantages of no mechanical parts and fast response. However, the wind speed and the energy efficiency of ionic wind generator are very low, which limit its application. In this paper, an ionic wind generator, constructed with needle-net electrode structure and powered by high-voltage positive dielectric current (DC) power supply, is built for cooling of a metal oxide semiconductor field effect transistor (MOSFET). The energy efficiency and wind speed of the ionic wind generator are optimized by adjusting the electrode structure and applied voltage amplitude. The results show that when the discharge spacing is fixed at 10 mm and the optimal needle spacing is 17.5 mm with 6 needles at 14 kV, the ionic wind velocity can reach a maximum value 3.20 m s−1 and the energy efficiency is 1.90%. Under optimal experimental conditions, the heat dissipation performance of MOSFET is significantly enhanced compared to using only a heat sink. With cooling by the ionic wind generator, the MOSFET junction temperature can be lowered by about 29 °C after 240 s operation.

Fast and flexible solid-state linear transformer driver for plasma discharge based on metal oxide semiconductor field effect transistor.

A pulsed power supply with a short rise time and high repetition frequency is favorable to driving diffusive plasma for strongly oxidizing radical (O3, OH) generation and increasing the system's energy efficiency. In this paper, a 10-stage solid-state linear transformer driver (LTD) with a nanosecond rise time is developed to drive plasma for wastewater treatment. To decrease the rise time, a control system with low jitter is developed to improve the synchronization of pulses using an optocoupler isolation chip. A 10-stage LTD with a rise time of 6.2ns is realized in the case that the rise time of the single-stage LTD is 5.4ns. The results show that the LTD can generate pulses on a 300Ω resistive load with a repetition frequency of 10kHz, an amplitude of 8.80kV, an overshoot less than 3.97%, and a reverse overshoot less than 4.82%. The rise time (6.2-33.0ns), the pulse width (35.9-200.0ns), and the fall time (10.5-27.6ns) can be adjusted flexibly and independently by controlling the drive signals of metal oxide semiconductor field effect transistors. The pulsed generator is utilized to drive plasma in the needle-water electrode system. The preliminary experimental results show that the plasma includes abundant oxygen atoms and hydroxyl radicals with high activity, and it is suitable for wastewater treatment.

Transient turn-on characteristics of Si RBDT and SiC MOSFET under nanosecond current pulse range

With the development of pulse power supplies, solid-state semiconductor switches are required to have fast switching speeds and low losses. Both Reverse blocking diode thyristor (RBDT) and silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) have fast turn-on speed, making them suitable candidates for short pulse generator. In this paper, the transient turn-on characteristics of Si RBDT and SiC MOSFET are analyzed theoretically and validated experimentally. Si RBDT and commercial 1.2 kV/81A SiC MOSFET are comparatively investigated in switching current pulse with a rise time of several hundreds of nanoseconds. (1) The anode current of RBDT could rise exponentially because of the latch-up effect of Si RBDT, while the drain current of SiC MOSFET tends to be saturated. (2) Utilizing the current rise time (Trise) to represent the switching speed, SiC MOSFET can switch faster when the current is lower than 400A. With the increase of the current, Si RBDT presents faster turn-on speed and lower switching loss due to the regenerative action of the two coupled transistors. (3) The transient characteristics of Si RBDT include a voltage-controlled inductance, while SiC MOSFET contains a current-controlled inductance based on the current rise time, respectively. With the increasing of the main voltage, the equivalent inductance of Si RBDT decreases and tends to be saturated when the main voltage is higher than half of the breakdown voltage of Si RBDT. For SiC MOSFET, the equivalent inductance increases until the drain current remains stable for a given gate voltage. This paper confirms the advantages of Si RBDT and SiC MOSFET in different situations.

Blocker tolerant cascode LNA for Wifi & IoT applications

SummaryWithin the domain of contemporary wireless communication systems, crafting Low‐Noise Amplifiers (LNA) holds a pivotal significance in achieving heightened signal sensitivity and comprehensive system efficacy and suppresses noise contributions from subsequent stages. Additionally, the low noise figure (NF) and high gain are critical LNA performance parameters in portable applications. Normally, LNA contains issues in noise performance, amplification, bandwidth, gain, and stability. To overcome these challenges, there must be a proper selection of transistors, harmonious impedance calibration, bias optimization, and circuit fine‐tuning. Moreover, metal oxide semiconductor field effect transistors (MOSFETs) are a popular choice in LNA design because of their excellent noise performance, high input impedance, complementary metal‐oxide semiconductor (CMOS) integration capabilities, low power operation, and suitability for a wide range of frequency applications. Through simulation and iterative enhancement, the LNA showcases remarkable Noise Figure, amplification, and linearity over a designated frequency span. This creation contributes to the advancement of radio frequency (RF) circuitry by designing an approach for LNA crafting that harmonizes conflicting prerequisites and unveils effective noise mitigation tactics. The outcomes emphasize the importance of a deliberated circuit architecture and parameter adjustment in accomplishing superlative LNA capabilities, rendering it fit for assimilation into diverse communication systems that demand minimal noise and heightened sensitivity.

A Brief Review of Single-Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide Power MOSFETs

Radiation hardening of power MOSFETs (metal oxide semiconductor field effect transistors) is of the highest priority for sustaining high-power systems in the space radiation environment. Silicon carbide (SiC)-based power electronics are being investigated as a strong alternative for high power spaceborne power electronic systems. SiC MOSFETs have been shown to be most prone to single-event burnout (SEB) from space radiation. The current knowledge of SiC MOSFET device degradation and failure mechanisms are reviewed in this paper. Additionally, the viability of radiation tolerant SiC MOSFET designs and the modeling methods of SEB phenomena are evaluated. A merit system is proposed to consider the performance of radiation tolerance and nominal electrical performance. Criteria needed for high-fidelity SEB simulations are also reviewed. This paper stands as a necessary analytical review to intercede the development of radiation-hardened power devices for space and extreme environment applications.

The Effects of a Gate Bias Condition on 1.2 kV SiC MOSFETs during Irradiating Gamma-Radiation.

We investigated the effects of gate bias regarding the degradation of electrical characteristics during gamma irradiation. Moreover, we observed the punch through failure of 1.2 kV rated commercial Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) due to the influence of gate bias. In addition, the threshold voltage (VT) and on-resistance (Ron) of the SiC MOSFETs decreased significantly by the influence of gate bias during gamma irradiation. We extracted the concentration of carriers and fixed charge (QF) in oxide using N-type SiC MOS capacitors and Transmission Line Measurement (TLM) patterns to analyze the effects of gamma irradiation. The Total Ionizing Dose (TID) effect caused by high-energy gamma-ray irradiation resulted in an increase in the concentration of holes and QF in both SiC and oxide. To analyze the phenomenon for increment of hole concentration in the device under gate bias, we extracted the subthreshold swing of SiC MOSFETs and verified the origin of TID effects accelerated by the gate bias. The QF and doping concentration of p-well values extracted from the experiments were used in TCAD simulations (version 2022.03) of the planar SiC MOSFET. As a result of analyzing the energy band diagram at the channel region of 1.2 kV SiC MOSFETs, it was verified that punch-through can occur in 1.2 kV SiC MOSFETs when the gate bias is applied, as the TID effect is accelerated by the gate bias.

Ferroelectric Based Low Power MOSFET for DC/RF Applications: Machine Learning Assisted Statistical Variation Analysis

The analog/radio-frequency (RF) performance of a ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET) with dielectric spacer was designed and proposed. The utilization of gate side wall spacers aims to mitigate short-channel effects (SCEs), and improve overall device performance. Simulation results demonstrate enhanced performance metrics, including improved transconductance (80%), reduced gate leakage (95.4%), and enhanced cutoff frequency (25%), making this design a promising candidate for next-generation high-performance analog and RF applications. Additionally, a novel machine learning (ML)-assisted approach is proposed for investigating the spacer-based FE-MOSFET to reduce the computational cost of numerical TCAD device simulations with the help of conventional- artificial neural network (C-ANN). This method is reported for the first-time ML-based C-ANN for Fe-based low-power MOSFET, matches the similar accuracy of physics-based TCAD with the fastest learning rate and fastest computational speed (in 95–100 s). An ML-based prediction replacement for physics-based TCAD is developed to save around 8–10 h of runtime for each iteration. Because ML predictions can never be 100% accurate, it is essential to ensure approximately zero mean-square error in the final results.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

Revolutionizing Technology with Spintronics: Devices and Their Transformative Applications

The scaling of metal oxide semiconductor field effect transistors (MOSFETs) for data storing and logic circuit operation has reached a critical point, beyond which further scaling poses various secondary issues. These problems include short channel effects, hot carrier effects (HCEs), and reliability concerns. However, a promising alternative called spintronics has recently emerged as a highly exciting technology. Spintronics considers both the charge and spin of electrons in device operations and offers superior properties compared to MOSFETs.Researchers have reported numerous spintronics devices that exhibit significant potential in memory and logic circuits when integrated with complementary metal oxide semiconductor (CMOS) technology. These devices not only possess excellent scalability but also consume less power than MOSFETs at the nano-scale level. This article aims to provide a comprehensive review of the current state, future prospects, and challenges associated with spintronics devices.

2-D Si0.8Ge0.2 source double-gate pocket PTFET for low power application: Modeling and simulation

To process 1-bit of information the small supply voltage (Vdd) and minimal leakage current are needed for transistors. Subthreshold swing (SS) of 60 mV/dec at 300 K is the basic bottleneck in metal oxide semiconductor field effect transistors. DFT in QuantumATK R-2020.09 was used to study Si0.8Ge0.2 band structure and band gap. A p-type tunnel field effect transistor (PTFET) was modeled employing the dual gate concept. Top gate has two metals; source and counter doped pocket are Si0.8Ge0.2. According to the proposed device simulation, the proposed device is showing excellent thermal stability for large on-current (Ion), weak off-current (Ioff), and weak ambipolar current (Iambi) at different temperatures. The proposed device achieves the Ion of 72.44 µA/µm and 3.2 µA/µm at supply voltage of −1 V and −0.5 V, respectively. At −0.5 V of Vdd, current ratio of Ion/Ioff is more than 1012, so device can be used for low power applications.

Comparative Study of Different High Voltage Switches Used in Pulsed High Voltage Application

High-voltage switches play a crucial role in pulsed power applications, where the efficient and reliable control of highvoltage pulses is required. This study aims to compare different types of high-voltage switches commonly used in pulsed power systems including electromechanical switches, vacuum switches, gas-filled switches, triggered spark gaps and solidstate switches. The comparison study focuses on key performance parameters such as voltage handling capability, current carrying capacity, turn-on time, and repetition rates are considered to provide a comprehensive study and analysis of the switch’s suitability for different pulsed power applications. Gas-filled switches such as spark gaps, thyratrons and ignitrons have been used in pulsed power systems due to their high voltage handling capability and low switching losses. However, they suffer from a limited lifetime and require maintenance and periodic replacement. Solid-state switches, i.e. Silicon-Controlled Rectifiers (SCRs), Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) offer advantages in terms of longevity, reliability, and reduced maintenance. However, they have limitations in high-voltage applications and exhibit higher switching losses. The findings of this comparison study will assist researchers, engineers, and system designers in selecting the most appropriate high-voltage switch for pulsed power applications, considering the specific requirements and constraints of the system. This will ultimately contribute to the advancement and optimization of pulsed power technologies across a wide range of scientific, industrial, and strategic applications.

Effect of Yttrium Treatment on Germanium-Oxide-Based Interfacial Layer of Ge P-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated Through in Situ Plasma-Enhanced Atomic Layer Deposition

Effect of Yttrium Treatment on Germanium-Oxide-Based Interfacial Layer of Ge P-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated Through in Situ Plasma-Enhanced Atomic Layer Deposition

Effect of Metal Oxide Semiconductor Field-Effect Transistor Output Parasitic Capacitance on Efficiency in Full-Bridge LLC DC/DC Converters.

This study analyzed the efficiency impact of a MOSFET output parasitic capacitance (Coss) on a full-bridge LLC DC/DC converter. The core of the converter was the control chip for a half-bridge LLC DC/DC converter, and the output signal of the chip controlled the first-arm power transistors of the primary side of the converter. The coupling transformer reversed the output signal to control the primary side of the second arm of the power transistor. The full-bridge converter comprises a half-bridge control chip that converts the high-voltage DC power supply to a low-voltage DC power supply, which is then synchronously rectified and supplied to the load. The primary side of the power transistor achieves a zero-voltage switching (ZVS) state through the resonance of the LLC converter. This design gives the converter high power density and a simple structure. Furthermore, to determine the appropriate output parasitic capacitance for improving converter efficiency, this study analyzed the effect of the output parasitic capacitance on the switching loss and conduction loss of the power transistor on the basis of the output parasitic capacitance of the primary-side power transistor. A 1200 W converter prototype was fabricated in this study, and when the output was 300 W, efficiency increased from 92.603% to 93.462%, a 0.859% increase. The empirical results verified the feasibility of the proposed theory.

CNTFET-based SRAM cell design using INDEP technique

As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube field effect transistor (CNTFET) has exhibited remarkable advantages compared to MOSFETs in circuit designs within the nanoscale range, owing to its extraordinary characteristics. In this work, a CNTFET-based six-transistor (6T) static random access memory (SRAM) cell is designed using the low power input-dependent (INDEP) technique. The suggested circuits' performance and efficiency is enhanced using CNTFET technology. The suggested design undergoes circuit simulations using the 32 nm CNTFET Stanford model. The results obtained from the simulations indicate that the suggested INDEP 6T SRAM cell surpasses both the conventional 6T SRAM cell and the previous designs in terms of power dissipation, delay, and energy efficiency. The hold, read, and write operations use less power, and the hold and write operations take less time to complete. The suggested design also demonstrates improved energy efficiency for hold and read operations compared to the conventional design. Furthermore, a stability analysis is conducted on the suggested INDEP 6T SRAM cell using the static noise margin (SNM) metric. The suggested INDEP approach in comparison to the other schemes has greater SNMs for hold, write, and read operations, indicating improved SRAM cell stability.

Performance comparison and analysis of silicon-based and carbon-based integrated circuits under VLSI

Since 1960, the semiconductor industry has invented Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Complementary Metal Oxide Semiconductor (CMOS) technologies. Subsequently, the semiconductor-based integrated circuit industry has led a new generation of information revolution, driving the rapid development of various electronic circuit technologies worldwide. With the physical limitations of the silicon semiconductor process, Moores Law is also approaching its physical limit. In the search for new semiconductor materials, carbon nanotube semiconductors have become one of the candidate materials for new semiconductor materials due to their many advantages, and their many characteristic parameters are even better than those of silicon semiconductors of the same size. This article introduces the research status, performance characteristics, and comparison of silicon-based and carbon-based integrated circuits, as well as the current application scenarios of silicon-based and carbon-based integrated circuits in the industry, and the many problems encountered. Finally, this article analyses the future development direction of the integrated circuit industry and the possible challenges it may face.

The Effect of Diluted N2O Annealing Time on Gate Dielectric Reliability of SiC Metal-Oxide Semiconductor Capacitors and Characterization of Performance on SiC Metal-Oxide Semiconductor Field Effect Transistor

We performed dry oxidation on n-type silicon carbide (SiC), followed by annealing in diluted N2O, and subsequently fabricated n-type MOS structures. The study aimed to investigate the impact of different annealing times on the trap charges near the SiC/SiO2 interface and the reliability of the gate dielectric. Capacitance-voltage (C-V) and current-voltage (I-V) measurements of the n-type MOS revealed that increasing the annealing time with N2O effectively reduces the density of electron traps near the SiC/SiO2 interface, mitigates the drift in flat-band voltage and enhances the oxide breakdown field strength. However, excessive annealing time leads to an increase in the flat-band voltage drift of the MOS, resulting in premature oxide breakdown. Using the optimized annealing conditions, we fabricated n-type LDMOSFETs and obtained the threshold voltage (Vth), field-effect mobility (μFE) and specific on-resistance (Ron-sp) from the transfer curve (Id-Vg) and output curve (Id-Vd) measurements. The research findings provide valuable insights for the gate oxidation process of SiC.

Modeling of non-intrinsic noise in nanometer metal oxide semiconductor field effect transistors

With the proportional reduction of metal–oxide–semiconductor field effect transistor (MOSFET) devices, the short channel effect, the parasitic effect, and the field strength effect are significantly enhanced, the proportion of parasitic resistance increases, and the non-intrinsic noise also increases, which seriously affects the working efficiency of the device. However, existing research mainly focuses on the intrinsic noise of MOSFET, and there is little research on the non-intrinsic noise; furthermore, the models describing the relationship between non-intrinsic noise, device structure, and bias have not yet been addressed. Therefore, in this paper, 90, 65, 32, 10, and 5 nm MOSFETs are studied. The rate of the intrinsic ballistic parameter is introduced to set up the source–drain current model and the non-intrinsic noise model. The source–drain current model is consistent with the theoretical model, numerical simulation, and experimental results in the literature. Finally, the relationship between the non-intrinsic noise and the bias and the device parameters are analyzed, and the conclusion is helpful to improve the working efficiency, lifetime, and response speed of nanoscale MOSFET devices.

Improving the Efficiency of an Isolated Bidirectional Dual Active Bridge DC–DC Converter Using Variable Frequency

This article presents a control method for an isolated bidirectional dual active bridge DC–DC converter (IBDC) where single phase shift (SPS) and variable frequency (VF) modulations are combined simultaneously with the purpose of improving the efficiency of the converter applied to the bidirectional charging of electric vehicles batteries. A complete power characterization of the dual active bridge (DAB) converter is carried out. The combined control achieves lossless turn-on and turn-off on the primary bridge for a wide range of output powers. A comparative study of power losses between the traditional SPS control and the combined method proposed here was also carried out. A prototype with an output power of 10 kW was built based on Silicon Carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFET), with which a peak efficiency close to 99% was obtained, thus verifying the viability of the method.

Research Progress on Metal-Oxide Semiconductor Field Effect Transistors

Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) have been constantly pursued in recent years as one of the indispensable components in modern electronic equipment, with better MOSFETs and a wider range of MOSFET applications. This study presents the classification and characteristics of MOSFETs briefly, investigates their applications in various aspects, and assesses the potential future development patterns of MOSFETs. This thesis research shows that different MOS tubes have different characteristics. MOSFETs mainly use enhanced N- and P-channel Metal-Oxide Semiconductor (NMOS and PMOS), complementary Metal-Oxide Semiconductor (CMOS), and neuronal Metal-Oxide Semiconductor (MOS). NMOS has the characteristics of less switching loss, a low threshold voltage, and is good for improving integration, but the temperature rises, etc. PMOS has the characteristics of being suitable for high-end drives and easy to drive and control, but the working speed is low and the switching loss is high. CMOS has the characteristics of good temperature stability, radiation resistance, and process complexity. Neuronal MOS can change the threshold voltage of the first input gate, and the floating gate charge can be preserved for a long time, so it is suitable for neural network applications. MOSFET can also be applied to switching and sensor applications. MOSFET applications generally belong to the fields of digital and analog circuits, communications, computers, etc. However, the application of MOS tubes in some fields still has defects. It is concluded that MOS tubes can be better used in other fields in the future, such as environmental monitoring and protection, chemical process control, etc. The future direction of MOS tubes includes higher performance, higher integration, fewer limitations, and so on. This thesis provides the direction for improvement of MOSFET research, which provides the basis and reference for subsequent research.