Metal-oxide-semiconductor Field-effect Transistors Research Articles

Thermomechanical Oriented Reliability Enhancement of Si MOSFET Panel-Level Packaging Fusing Ant Colony Optimization With Backpropagation Neural Network

Considerable advancements in power semiconductor devices have resulted in such devices being increasingly adopted in applications of energy generation, conversion, and transmission. Hence, we proposed a Fan-Out Panel-Level Packaging (FOPLP) design for 30V Si based Metal Oxide Semiconductor Field Effect Transistor (MOSFET). To achieve superior reliability of the packaging, we applied the Nondominated Sorting Genetic Algorithm with elitist strategy (NSGA-II) and Ant Colony Optimization–Backpropagation Neural Network (ACO–BPNN) to optimize the design of redistribution layer (RDL) in FOPLP. We first quantified the thermal resistance and thermo-mechanical coupling stress of the designed package under thermal cycling loading. Next, NSGA-II and ACO–BPNN were used to optimize the size of the RDL blind via. Finally, the effectiveness of the proposed reliability optimization methods was verified by performing thermal shock reliability ageing tests on the prepared devices.

Hybrid Si/SiC Switches: A Review of Control Objectives, Gate Driving Approaches and Packaging Solutions

Hybrid silicon (Si)/silicon carbide (SiC) switches are gaining increased attention for designing high-efficiency and high-power density energy conversion systems. They offer very good conduction and switching power loss performance compared to using only Si insulated gate bipolar transistor (IGBT) or SiC metal–oxide–semiconductor field effect transistor (MOSFET) devices as a result of combining the best properties of both devices. Several Si/SiC gate control strategies, gate driving approaches, and packaging considerations have been proposed in the literature. This article presents a comprehensive review and performance comparison of different Si/SiC gate control strategies, gate driver solutions, and packaging approaches that are already proposed in the literature. In addition, it aims to provide a general guideline for selecting the appropriate Si/SiC gate control approach that is suitable for different applications considering several Si/SiC switch design properties. It also aims to establish a general metrics for evaluating the performance of different Si/SiC gate driver solutions that are proposed in the literature in order to help the designer choose a suitable gate driver solution for different applications. Moreover, it highlights future research and development needs of hybrid Si/SiC switches in terms of gate control techniques, gate driver approaches, and packaging solutions in order to achieve further performance improvements and fully exploit their benefits.

An Electric Field Probe With High Immunity for SiC MOSFET Switching Voltage Measurement

Accurate measurement of switching voltage is the basis for evaluating the dynamic behavior of power devices. With the development of wide bandgap (WBG) devices, the high switching speed of the silicon carbide metal–oxide–semiconductor field-effect transistors (SiC MOSFETs) imposes high bandwidth and strong immunity requirements on the voltage probe. The electric field probe (EFP) based on the principle of electric field coupling has a naturally high bandwidth, which can be considered as a potential competitor. However, due to the noncontact suspended measurement method, the interference signal is easily coupled by the EFP and affects the measurement accuracy. Thus, this article proposes a high noise-immune structure for EFP to implement the measurement of SiC MOSFET switching voltage. The EFP is manufactured from the printed circuit board (PCB), which can provide a more accurate parameter design. Then, the shielded copper clad and via arrays structures are proposed, and the effectiveness of the shielding structure is verified by adding an interference source. Finally, through the double-pulse test, it is demonstrated that the performance of the proposed EFP is sufficient to measure the switching voltage of SiC MOSFETs.

Lifetime of photoexcited carriers in space-controlled Si nanopillar/SiGe composite films investigated by a laser heterodyne photothermal displacement method

Thermal management has become more critical as semiconductor devices are miniaturized. In metal–oxide–semiconductor field-effect transistors, the problem is the reduction in electron mobility in the channel layer owing to the temperature rise caused by heat generation near the channel-drain region. Focusing on the mean free paths of phonons and electrons in Si, nanostructures of a few 10 nm may only hinder heat propagation without affecting electron transportation. Therefore, inserting nanostructures into the channel layer may prevent a temperature rise and maintain a higher electron mobility. To discuss the relationship between the spacing between the nanopillars (NPs) and the heat generation and carrier behavior of the Si-NP/SiGe composite film, samples with NP spacings of 13, 27, or 47 nm were prepared. We previously confirmed that the thermal conductivity of the Si-NP/SiGe composite film decreased as NP spacing narrowed. The NPs scattered phonon propagation and suppressed heat propagation. However, carrier transport properties such as electrical conductivity, carrier mobility, and carrier lifetime have never been discussed. The laser heterodyne photothermal displacement method was used to examine the effect of nanostructures on carrier mobility and carrier lifetime of Si-NP/SiGe composite films. We observed that the carrier lifetime became longer when the NP spacing was comparable to the electron mean-free path of approximately 27 nm.

Design and Implementation of a Paralleled Discrete SiC MOSFET Half-Bridge Circuit with an Improved Symmetric Layout and Unique Laminated Busbar

Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) have many advantages compared to silicon (Si) MOSFETs: low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency. As a result, Si MOSFETs are replaced with SiC MOSFETs in many industrial applications. However, there are still not as many SiC modules to customize for each application. To meet the high-power requirement for custom applications, paralleling discrete SiC MOSFETs is an essential solution. However, it comes with many technical challenges; inequality in current sharing, different switching losses, different transient characteristics, and so forth. In this paper, the detailed MATLAB®/Simulink® Simpscape model of the SiC MOSFET from the datasheet and the simulation of the half-bridge circuit are investigated. Furthermore, this paper proposes the implementation of the four-paralleled SiC MOSFET half-bridge circuit with an improved symmetric gate driver layout. Moreover, a unique laminated busbar connected directly to the printed circuit board (PCB) is proposed to increase current and thermal capacity and decrease parasitic effects. Finally, the experimental and simulation results are presented using a 650 V SiC MOSFET (CREE) double-pulse test (DPT) circuit. The voltage overshoot problems and applied solutions are also presented.

FinFET based photoreceptor for silicon retina to reduce power consumption

In this paper, we propose a SOI FinFET device based photoreceptor for silicon retina to reduce power consumption. Nowadays, in the field of neuromorphic engineering the main aim of the researcher is to implement a biological nervous system based on silicon devices. Major performance metrics which influence the design of neuromorphic circuits along with biological plausibility are compactness, low power consumption, scalability and computational complexity. Moreover, to process the information biologically billions of neurons consume only a few watts of power. However, present design of silicon photoreceptor consumes power much larger than actual biological photoreceptor. Hence to achieve low power consumption we are using nanometer SOI FinFET device technology. In this paper, output of the outer retinal cell, namely photoreceptors, is reconstructed and verified with the help of developed ionic current based mathematical model of the retina. The model contains non-linear differential equations based on the fundamental framework of the Hodgkin-Huxley model. In order to closely match the biological response, the selection of parameters of membrane voltage and other membrane dependencies through compartments are done using MATLAB simulation. After mathematical verification, the biological behavior of photoreceptor cell of retinal system is mimicked through circuit using 180 nm Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and 32 nm Silicon on Insulator Fin Field Effect Transistor (SOI FinFET) device. It is observed that SOI FinFET based photoreceptor for silicon retina circuit consumes less power in picowatts matching the power consumption of biological retinal system, as compared with MOSFET based circuits.

Low temperature atomic hydrogen annealing of InGaAs MOSFETs

Recent work showing a strong quality improvement of the Si/SiO2 material system by low temperature atomic hydrogen annealing (AHA), and the fact that III–V semiconductors outperform Si in many applications makes the investigation of AHA on III–V/high-k interfaces to a very interesting topic. In this work, the potential of AHA as a low temperature annealing treatment of InGaAs metal–oxide–semiconductor field-effect transistors is presented and compared to conventional annealing in a rapid thermal process (RTP) system using forming gas. It is found that post metal annealing in atomic hydrogen greatly enhances the quality of the metal–oxide–semiconductor structure in terms of effective mobility, minimum subthreshold swing, and reliability. The device performance is comparable to RTP annealing but can be performed at a lower temperature, which opens up for integration of more temperature-sensitive materials in the device stack.

Reliability analysis based on the Wiener process integrated with historical degradation data

AbstractFor high‐reliability and long‐life electronic devices, reliability analyses based on degradation data with small sample sizes are an outstanding question. Recently, increasing attention has been paid to the abundant historical degradation data. Exploiting the information in these historical data efficiently and integrating them to benefit the current reliability analysis is an important issue. This study proposes a new integrating method for the historical and current degradation data based on the Wiener process by considering the consistency of failure mechanisms between the different batches of degradation data. Simulation studies show that the new method has superior reliability estimation, and is robust to the assumption of consistent failure mechanisms. Finally, the proposed method is used to analyze a real data set consisting of the metal‐oxide‐semiconductor field‐effect transistor (MOSFET) degradation data.

The effect of gate geometric effect and polysilicon doping on the performance of scaled NMOS

Insufficiently high doping in polysilicon gates of metal oxide semiconductor field effect transistor (MOSFET) becomes unavoidable due to the demands for low-energy ion implantation and limited annealing conditions to achieve ultra-shallow source and drain junctions. This results in the poly-depletion effect for ultra-thin MOSFET, loss of current drive and shift in the threshold voltage. This problem gets intense when the device is further scaled down for the gate length and thickness of gate oxide. Hence, our current work focuses on the effect of gate geometrical effect and polysilicon gate doping on scaled n-channel MOSFET(NMOS) performance. The NMOS device was constructed using TCAD ATLAS tools from SILVACO software. Six different gate lengths of 0.6 μm, 0.4 μm, 0.2 μm, 60 nm, 40 nm and 20 nm were set, and the n-type doping concentration in the polysilicon gate was varied to 1× 1018, 1× 1020 and 1 × 1021 cm-3 respectively to see their effect on the NMOS I-V and C-V performances. The findings showed that as the gate length is scaled down, the drain current increases, and as the concentration of the polysilicon doping increases, the value of the threshold voltage, VTH decreases. Based on the simulation and data collected, it can be concluded that the optimum concentration of polysilicon doping that can reduce the poly-depletion effect is 1 × 1021 cm-3, and the optimum gate length that can be used to overcome the problem is 20 nm.

Cascaded SiC JFET Topology for High-Voltage Solid-State Circuit Breaker Applications

With evolving landscape of direct current (DC) power transmission and distribution, a reliable and fast protection against faults is critical. High performance DC solid-state circuit breakers (SSCBs) can be designed using silicon carbide (SiC) junction field-effect transistors (JFETs), which utilize the device's intrinsic normally-ON characteristic and low ON-resistance. However, for SSCB that require high-voltage (HV) blocking capability, a proper number of JFETs need to be connected in series to achieve the desired voltage blocking rating. It has been conventional to add a controlling normally-OFF transistor, such a metal-oxide-semiconductor field-effect transistor (MOSFET), resulting in a circuit with normally-OFF behavior. However, disparities both in the voltage rating and in the ON-resistance between MOSFETs and JFETs tend to complicate the circuit design, and physically, they may lead to serious localized thermal stresses. A significant challenge remains with ensuring equal voltage balancing across the JFETs during the switching transitions as well as the blocking stage as it is crucial to prevent permanent damages from over-voltage stresses. Therefore, this article presents a new switch topology, in which a cascaded JFET configuration is operated without using a control MOSFET or other added control device. The dynamic voltage balancing network to synchronize both the JFETs' turn ON and OFF intervals is described analytically. Moreover, a novel static voltage balancing network is proposed to establish equal sharing of the total blocking voltage across the series connection of JFETs while maintaining low power loss.

New Methodology for the Design of Nanostructured Integrated Circuits

Background: A metal oxide semiconductor field effect transistor (MOSFET) is widely used to make integrated circuits (ICs). MOSFET devices are reaching the practical limitations for further scaling in the nanoscale regime. It motivates the researchers to explore and develop new ways to advance the electronics industry. Quantum-dot cellular automata (QCA) is a potential way to replace the MOSFET devices in the nanoscale regime. QCA nanotechnology not only solves the issue of scalability but also degrades the leakage current. It has numerous benefits, such as a highly dense design, fast speed, and energy efficiency compared to complementary metal-oxide-semiconductor (CMOS) technology. Objective: An extensive study of QCA nanotechnology is needed to quickly understand the field. Optimizing the QCA designs is the mandatory requirement to minimize the occupied cell area, latency and quantum cost. The preliminary knowledge of QCA nanotechnology boosts the idea of generating different logic functions. This review paper presents the methodology for making the fundamental logic gates using QCA nanotechnology. XOR gate is commonly used to implement popular circuits such as adders, subtractors, comparators, code converters, reversible gates etc. The various available QCA-based 2-input XOR gate designs are discussed and compared for the different performance metrics. Methods: Columbic interaction causes logical operations, and data is transferred from one cell to another cell using cell-to-cell interaction. A specific arrangement of QCA cells produces a specific logic. QCA Designer tool using a Bi-stable simulation engine is used to design different digital circuits. Results: This review paper deals with the design of the 2-input XOR gate. The considered performance metrics for the comparison purpose are cell count, occupied area, clock cycle, and quantum cost. Existing works on 2-input XOR gates show that a minimum of 8 QCA cells are needed for a 2-input XOR gate using QCA nanotechnology. A single clock cycle-based 2-input XOR gate requires at least 9 QCA cells. The quantum cost can be minimized by reducing the number of QCA cells and clock cycles. Conclusion: This review paper helps the circuit designers to select the appropriate 2-input XOR gate for the design of complex circuits. Circuit designers can use the fundamental concepts detailed in the paper to implement any Boolean function and optimize it for the existing designs. A researcher had developed a 2-input XOR gate using only 8 QCA cells with 0.50 clock cycles. Therefore, designers can start from here to further optimize the 2-input XOR gate with a single clock cycle.

Comparisons and Evaluations of Silicon and Wide Band Gap Devices at Cryogenic Temperature

In this article, the static and dynamic characterizations for semiconductors with different materials, including silicon (Si), silicon carbide (SiC), and gallium nitride (GaN), are evaluated and compared at room temperature and cryogenic temperature (liquid nitrogen temperature). For static characterizations, the on-state resistance and threshold voltage are evaluated. For dynamic characterizations, the turn-on switching loss, turn-off switching loss, and dynamic on-state resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds(on)</sub> ) are evaluated. The results demonstrate that Si and GaN based semiconductors have improved performances with lower on-state resistance and faster switching speed at low temperature operations. For SiC based semiconductors, the on-state resistance increases significantly at cryogenic temperature. The switching speed is reduced dramatically for the evaluated 1.2 kV SiC metal oxide semiconductor field effect transistors (MOSFETs) at cryogenic temperature. This makes it less attractive for cryogenic applications. For the evaluated 650 V and 900 V SiC MOSFETs, the switching speed remains almost unchanged at low temperature. GaN high electron mobility transistor (HEMT) demonstrates a fast turn-on switching speed at low temperature, where the device's <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di/dt</i> are almost doubled when compared with room temperature. In addition, the dynamic <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds(on)</sub> of the evaluated GaN HEMTs also decreases at low temperatures. The evaluation results can serve as guidelines for cryogenic power electronics applications. Meanwhile, the future work for semiconductors cryogenic characterizations is discussed.

Self-aware artificial auditory neuron with a triboelectric sensor for spike-based neuromorphic hardware

Auditory organs can detect and process sounds with the help of the organ of Corti located in the cochlea. The energy efficiency of biological processing for an input sound signal is very high due to the spike-based auditory neurons in auditory organs. Here, inspired by the biological auditory system, a self-aware artificial auditory neuron module is constructed by serially connecting a triboelectric nanogenerator (TENG) and a bi-stable resistor (biristor). The TENG serves as a sound sensor and a current source to feed current input so as to awaken the biristor, which acts as a device-level neuron that is dissimilar to a traditional circuit-based neuron. The proposed self-aware artificial neuron module simultaneously detects the sound pressure level (SPL) and encodes it into a spike form, after which it transmits these data to an artificial synapse as an input neuron for a spiking neural network (SNN). Like an auditory organ, the spiking frequency of the bio-inspired artificial neuron increases when the SPL increases. In addition, the self-aware artificial auditory system with a single-layer perceptron (SLP) for SNN is demonstrated for musical pitch classification. This artificial auditory system is configured by combining two artificial auditory neuron modules and four metal-oxide-semiconductor field-effect transistor (MOSFET) synapses. The biristor neuron and the MOSFET synapse are structurally identical but electrically different. Two artificial auditory neuron modules correspond to two different frequencies. This artificial auditory system distinguishes two sounds from a piano. It also identifies two similar sounds from a cello and a violin. The proposed artificial SNN-based auditory system is advantageous for low power consumption due to the event-driven spiking transmission scheme. The improved energy efficiency with the SNN as described here is attributed to the self-aware sensing capability for sound signals. Therefore, the self-aware SNN auditory system given its low power consumption is promising for a remote sensor, a wireless sensor, and for an Internet of Things (IoT) sensor system.

The cascode configuration of a GaN static induction transistor for MHz power switch applications

A cascoded gallium nitride (GaN) static induction transistor (SIT) that combines a low-voltage Si metal-oxide-semiconductor field-effect transistor (MOSFET) at the input and a high-voltage GaN SIT at the output has been simulated and evaluated. The Schottky-gate SIT is an ideal choice for the cascode configuration as it provides a parallel Schottky diode, enabling bi-directional conduction. Simulation results show that the device has great potential for MHz frequency switching applications. Additionally, power losses in the Si MOSFET and GaN SIT have been analyzed separately.

Analysis of single event effects by heavy ion irradiation of Ga2O3 metal–oxide–semiconductor field-effect transistors

The model of lateral β-Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET) was established using Sentaurus Technology Computer Aided Design software. The gate-to-drain distance of the device was 13.7 μm, and the breakdown voltage was 1135 V. The single event effect simulation model caused by heavy ion irradiation was introduced, and the effects of heavy ions’ incident position, angle, drain bias voltage, and linear energy transfer on the single event effect were studied. It is found that x = 7.7 μm is the sensitive location of the single event effect at the gate corner near the drain side and the peak value of the transient current is 177 mA/mm. The effect of the terminal structure of the field plate on the transient effect of the single event effect of β-Ga2O3 MOSFET is studied. It is also found that the sensitive position of the single event effect of the conventional structure, gate-field plate structure, and gate–source composite field plate structure is around x = 7.7 μm when VDS = 10 V. The peak transient currents obtained are 177, 161, and 148 mA/mm. The single event effect pulse current of the three structures increases with an increase in the drain bias voltage, while the peak pulse current of the conventional structure is larger than that of the gate-field plate structure and the gate–source composite structure. The research shows that the terminal structure of the field plate is reliable means to reduce the single particle effect.

Proton induced radiation effect of SiC MOSFET under different bias

Radiation effects of silicon carbide metal–oxide–semiconductor field-effect transistors (SiC MOSFETs) induced by 20 MeV proton under drain bias (V D = 800 V, V G = 0 V), gate bias (V D = 0 V, V G = 10 V), turn-on bias (V D = 0.5 V, V G = 4 V) and static bias (V D = 0 V, V G = 0 V) are investigated. The drain current of SiC MOSFET under turn-on bias increases linearly with the increase of proton fluence during the proton irradiation. When the cumulative proton fluence reaches 2 × 1011 p⋅cm−2, the threshold voltage of SiC MOSFETs with four bias conditions shifts to the left, and the degradation of electrical characteristics of SiC MOSFETs with gate bias is the most serious. In the deep level transient spectrum test, it is found that the defect energy level of SiC MOSFET is mainly the ON2 (E c – 1.1 eV) defect center, and the defect concentration and defect capture cross section of SiC MOSFET with proton radiation under gate bias increase most. By comparing the degradation of SiC MOSFET under proton cumulative irradiation, equivalent 1 MeV neutron irradiation and gamma irradiation, and combining with the defect change of SiC MOSFET under gamma irradiation and the non-ionizing energy loss induced by equivalent 1 MeV neutron in SiC MOSFET, the degradation of SiC MOSFET induced by proton is mainly caused by ionizing radiation damage. The results of TCAD analysis show that the ionizing radiation damage of SiC MOSFET is affected by the intensity and direction of the electric field in the oxide layer and epitaxial layer.

Synergistic effect of total ionizing dose on single-event gate rupture in SiC power MOSFETs

The synergistic effect of total ionizing dose (TID) and single event gate rupture (SEGR) in SiC power metal–oxide–semiconductor field effect transistors (MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.

Comparative study on short-circuit and surge current capabilities of 1.2 kV SiC SBD-embedded MOSFETs

This paper presents a comparative study on the short-circuit and surge current withstanding capabilities and the static and turn-on switching characteristics of commercial 1.2 kV SiC Schottky barrier diode (SBD)-embedded metal–oxide–semiconductor field-effect transistors (MOSFETs). The results confirmed that MOSFETs with a larger SBD area ratio had higher leakage current through the SBD during short-circuit transients due to a higher electric field and lattice temperatures as high as roughly 1120 K at the SBD, which resulted in reduced short-circuit withstanding capabilities. It was also found that MOSFETs with a smaller SBD area ratio had reduced surge-current capabilities in embedded SBDs. We conclude that is not due to the small SBD area ratio but to a weak bipolar operation of the Junction Barrier and Schottky rectifiers even in high current regions.

Impact of low-dose radiation on nitrided lateral 4H-SiC MOSFETs and the related mechanisms

Lateral type n-channel 4H-SiC metal--oxide--semiconductor field effect transistors (MOSFETs), fabricated using a current industrial process, are irradiated with gamma rays at different irradiation doses in this paper to carry out a profound study on the generation mechanism of radiation-induced interface traps and oxide trapped charges. Electrical parameters (e.g., threshold voltage, subthreshold swing and channel mobility) of the device before and after irradiation are investigated, and the influence of the channel orientation ( and ) on the radiation effect is discussed for the first time. A positive threshold voltage shift is observed at very low irradiation doses (< 100 krad (Si)); the threshold voltage then shifts negatively as the dose increases. It is found that the dependence of interface trap generation on the radiation dose is not the same for doses below and above 100 krad. For irradiation doses < 100 krad, the radiation-induced interface traps with relatively high generation speeds dominate the competition with radiation-induced oxide trapped charges, contributing to the positive threshold voltage shift correspondingly. All these results provide additional insight into the radiation-induced charge trapping mechanism in the SiO2/SiC interface.

A SiC asymmetric cell trench MOSFET with a split gate and integrated p+-poly Si/SiC heterojunction freewheeling diode

A new SiC asymmetric cell trench metal–oxide–semiconductor field effect transistor (MOSFET) with a split gate (SG) and integrated p+-poly Si/SiC heterojunction freewheeling diode (SGHJD-TMOS) is investigated in this article. The SG structure of the SGHJD-TMOS structure can effectively reduce the gate-drain capacitance and reduce the high gate-oxide electric field. The integrated p+-poly Si/SiC heterojunction freewheeling diode substantially improves body diode characteristics and reduces switching losses without degrading the static characteristics of the device. Numerical analysis results show that, compared with the conventional asymmetric cell trench MOSFET (CA-TMOS), the high-frequency figure of merit (HF-FOM, R on,sp × Q gd,sp) is reduced by 92.5%, and the gate-oxide electric field is reduced by 75%. In addition, the forward conduction voltage drop (V F) and gate-drain charge (Q gd) are reduced from 2.90 V and 63.5 μC/cm2 in the CA-TMOS to 1.80 V and 26.1 μC/cm2 in the SGHJD-TMOS, respectively. Compared with the CA-TMOS, the turn-on loss (E on) and turn-off loss (E off) of the SGHJD-TMOS are reduced by 21.1% and 12.2%, respectively.