Metal-oxide-metal Capacitors Research Articles

A Data Weight Averaging-Inspired Digital Calibration Method for a 10-Bit Noise-Shaping Successive Approximation Register

This paper presents a digital calibration method for a 10-bit noise-shaping Successive Approximation Register Analog to Digital Converter (SAR ADC). The proposed calibration method is inspired by its Data Weight Averaging (DWA) counterpart, but stays static, while achieving a similar Integral Nonlinearity (INL) and 1.3 dB better Signal-to-Noise Ratio (SNR) in measurements without oversampling. This advantage in SNR holds until an Oversampling Ratio (OSR) of 2 for the proposed method, which also saves 50 % power. At a 1.2 V power supply, the ADC consumes a power of 70 µW at a conversion rate of 50 kHz. Fabricated using 55 nm Complementary Metal Oxide Semiconductor (CMOS) Metal-Oxide-Metal Capacitor (MOMCAP) technology, it occupies an active area of 370 µm × 350 µm, when achieving an INL of 0.3 Least Significant Bit (LSB) and an SNR of 66.9 dB at an OSR of 8.

An 11.6aF/kPa Mechanical Stress Sensor With 0.808% Temperature-Drift Oscillator for Flip-Chip Packaging

During the package processes, including chip attachment and encapsulation, the stress caused by the thermal and mechanical load is usually generated in integrated circuit chips. This brief developed a mechanical stress sensor in a standard 180nm CMOS process for runtime stress measurement. The contributions done in this brief are summarized as follows: 1) A temperature-compensation RC oscillator circuit converts the warpage of the die induced by the mechanical stress into the frequency output. It even can measure the thermally induced stresses with a wide temperature range. The oscillator has a frequency variation of −0.808% from temperature stability measurements from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 40^{\circ }\text{C}$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$120^{\circ }\text{C}$ </tex-math></inline-formula> . 2) Rather than the complicated calibrations and advanced measurement equipment, the frequency can be easily measured with the chip area less than 0.569 mm2 and the power consumption less than 22.9 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> . 3) As for the sensing array, the sensitivity and stability of the metal-insulator-metal (MIM) and metal–oxide–metal (MOM) capacitors are verified. The measured average sensitivity of the test chip using a MIM capacitor with 0.1736 Hz/kPa is more sensitive than that using a MOM capacitor with 0.102 Hz/kPa. The linear fit curves of the output frequency have the coefficient of determination ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{R}^{2}$ </tex-math></inline-formula> ) of 0.9983 for MIM and 0.9959 for MOM, indicating an excellent linear response of the sensor circuit.

`Failure analysis of short-circuit failure of metal-oxide-metal capacitor

Metal-oxide-metal (MOM) capacitors are used widely in semiconductor integrated circuits. This study describes a method for failure analysis of MOM capacitor short-circuit. We present two case examples to highlight the significance of this method. Various techniques are described, such as thermal emission microscopy (ThEM), beam induced resistance change (OBIRCH), photoemission microscopy (PEM), focused ion beam (FIB), and passive voltage comparison (PVC). ThEM could be an effective alternative, albeit with low magnification. OBIRCH could help verify the defect location in the MOM structure, albeit with a large region of interest (ROI). The application of PEM based on an InGaAs detector can reduce the ROI and yield satisfactory fault isolation results. PVC can indicate the metal bridge phenomenon and help guide FIB cross-sectional analysis. To summarize, our observations indicate that PEM and PVC are effective alternatives for the failure analysis of MOM short-circuit failure.

High-Q On-Chip Capacitors Featuring “Self-Inductance Cancellation” for RF and mm-Wave Applications

In this letter, we are reporting on the characterization of the on-chip metal–oxide–metal (MOM) capacitors that use “self-inductance cancellation” technique resulting in high-performance operation in radio frequency (RF)/millimeter-wave (mm-wave) regime. The utilized method helps mitigate the mutual magnetic induction between the metal fingers of a MOM capacitor while they are placed in proximity to each other, by controlling the direction of the RF current flow. More than two times inductance cancellation is achieved, thus resulting in an increase of the self-resonance frequency and quality factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -factor) of the RF capacitor. The test structures are fabricated using Intel 16 FinFET technology, where postsilicon data show a good agreement between the theory and simulation. This methodology is CMOS compatible and is applicable to RF/mm-wave circuits that employ RF capacitors toward improving the RF system performance.

Modeling of High-Q Conical Inductors and MOM Capacitors for Millimeter- Wave Applications

Conical inductors and metal-oxide-metal (MOM) capacitors are shown to have higher qualityfactor (Q) characteristics at millimeter wave (mm-wave) frequencies over conventional inductors and nitride MIM capacitors. In this work, Physics-basedanalytical models are developed for conical inductors and MOM capacitors usable at mmwave frequencies. The linear voltage profile along the turns of the conical inductor is taken into account for capacitance calculation which is critical in accurately predicting Q-values. Two RL networks coupled by capacitors are proposed to capture the frequency-dependent characteristics of the MOM capacitor. The lumped elements in both these device models are frequency independent and can be calculated using layout and process parameters. The proposed models for conical inductors and MOM capacitors are verified with electromagnetic (EM) simulations till 100 GHz. A prototype 60-GHz bandpass filter (BPF) is fabricated using 0.18 μm RF-silicon on insulator (SOI) technology to validate the accuracy of the developed compact models. BPF simulation results using the proposed models are shown to be in excellent agreement with those produced with EM simulations and silicon measurements.

Single-Event Upset Responses of Metal–Oxide–Metal Capacitors and Diodes Used in Bulk 65-nm CMOS Analog Circuits

The focus of this article is to characterize the behavior of metal–oxide–metal (MOM) capacitors when used in a switched-capacitor circuit in a standard 65-nm 1.2-V CMOS technology subject to ionizing radiation. The goal is twofold: first, to understand radiation-induced single-event effects on a fundamental building block of analog circuits unconstrained by a particular application and second, to explore the capacitor’s use as a particle detector analogous to the diode active-pixel sensor. The single-event signal response from the diode and MOM capacitor structures were consistent with ionization; the behavior of the diode was consistent with previously published results. The diode single-event signal response exhibited a step-like waveform, whereas the MOM capacitor exhibited an exponential-decay waveform, thus indicating different detection mechanisms where liberated charges were, respectively, either collected or not collected.

A Capacitor Dielectric Relaxation Effect Cancellation Circuit in a 12-Bit, 1-MSps, 5.0-V SAR ADC on a 28-nm Embedded Flash Memory Microcontroller

In this letter, the influence on an analog-to-digital converter (ADC) of the dielectric relaxation effect of a metal-oxide-metal (MOM) capacitor is described, agreement of a capacitance model with simulations is shown, and a circuit for canceling the dielectric relaxation effect is proposed. When using an MOM capacitor that exhibits dielectric relaxation in an SAR-ADC for an MCU, accuracy is degraded by switching between multiple analog inputs due to the slow charge and discharge components in the capacitors. In this letter a circuit is proposed in which, by applying the same voltage stress on a local DAC at the negative side input of a comparator as on that at the positive one which samples the single-ended input and performs bit decisions, the influence of the dielectric relaxation effect is converted into common mode error and can be canceled by a differential-input comparator. This ADC is fabricated in a 28-nm embedded flash memory process, and in operation at 5 V and 1 MSps achieves an absolute accuracy error of -1.69/1.38 LSB, an INL of -0.50/0.65 LSB, and a DNL of -0.40/0.28 LSB without being affected by dielectric relaxation.

Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters

As technology advances, smaller feature size enables layout precision in the lateral direction. In contrast to traditional metal–insulator–metal capacitors, metal–oxide–metal (MOM) capacitors are generally of higher density and consume less area, because they adopt a 3-D topology over several metal layers to use lateral field capacitance. To achieve little area consumption, MOM capacitors require new layout methods with routing even before placement. Since the routing wires are of comparable size to unit capacitors in MOM design, routing-induced parasitic capacitance must also be considered. To obtain a higher yield, common-centroid layout style and high dispersion of cells are desired. This paper introduces a new vertical bars structure for binary weighted MOM capacitor arrays and presents a new method to generate common-centroid regular-structured layouts with mismatch reduction and routing-parasitic-matching consideration. Experimental results show that the presented approach generates high-density, low-powered, and highly accurate ratioed capacitors.

A frame-based EM-simulation for design ofLCoscillator with MoM capacitor banks

This article presents a simulation method for the design of a digitally controlled oscillator (DCO). Electromagnetic (EM) simulations are essential and inevitable for modern LC oscillator design. Although EM-simulators provide high accuracy, the EM-simulation time is very long when metal-oxide-metal (MoM) capacitors are present. The proposed frame-based EM-simulation can significantly reduce the EM-simulation time even in the presence of MoM capacitors without influencing the accuracy. To verify the proposed method, a DCO was fabricated using a 55-nm CMOS process. Measurements of the DCO are in good agreement with the frame-based post-layout simulation results. In addition, the DCO has good performances with a low power consumption of approximately 0.68 mW.

Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors

Small metal-oxide-metal (MOM) capacitors are essential to energy-efficient mixed-signal integrated circuit design. However, only few reports discuss their matching properties based on large sets of measured data. In this paper, we report matching properties of femtofarad and sub-femtofarad MOM vertical-field parallel-plate capacitors and lateral-field fringing capacitors. We study the effect of both the finger-length and finger-spacing on the mismatch of lateral-field capacitors. In addition, we compare the matching properties and the area efficiency of vertical-field and lateral-field capacitors. We use direct mismatch measurement technique, and we illustrate its feasibility using experimental measurements and Monte Carlo simulations. The test-chips are fabricated in a 0.18 $\mu\text{m}$ CMOS process. A large number of test structures is characterized (4800 test structures), which improves the statistical reliability of the extracted mismatch information. Despite conventional wisdom, extensive measurements show that vertical-field and lateral-field MOM capacitors have the same matching properties when the actual capacitor area is considered. Measurements show that the mismatch depends on the capacitor area but not on the spacing; thus, for a given mismatch specification, the lateral-field MOM capacitor can have arbitrarily small capacitance by increasing the spacing between the capacitor fingers, at the expense of increased chip area.

A capacitive DAC with custom 3-D 1-fF MOM unit capacitors optimized for fast-settling routing in high speed SAR ADCs

Asynchronous successive approximation register (SAR) analog-to-digital converters (ADC) feature high energy efficiency but medium performance. From the point of view of speed, the key bottleneck is the unit capacitor size. In this paper, a small size three-dimensional (3-D) metal—oxide—metal (MOM) capacitor is proposed. The unit capacitor has a capacitance of 1-fF. It shapes as an umbrella, which is designed for fast settling consideration. A comparison among the proposed capacitor with other 3-D MOM capacitors is also given in the paper. To demonstrate the effectiveness of the MOM capacitor, a 6-b capacitive DAC is implemented in TSMC 1P9M 65 nm LP CMOS technology. The DAC consumes a power dissipation of 0.16 mW at the rate of 100 MS/s, excluding a source-follower based output buffer. Static measurement result shows that INL is less than ±1 LSB and DNL is less than ±0.5 LSB. In addition, a 100 MS/s 9-bit SAR ADC with the proposed 3-D capacitor is simulated.

Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit

Between the metal–insulator–metal (MIM) capacitor and metal–oxide–metal (MOM) capacitor, the MIM capacitor has a better characteristic of stable capacitance. However, the MOM capacitors can be easily realized through the metal interconnections, which does not need additional fabrication masks into the process. Moreover, the capacitance density of the MOM capacitor can exceed the MIM capacitor when more metal layers are used in nanoscale CMOS processes. With advantages of lower fabrication cost and higher capacitance density, the MOM capacitor could replace MIM capacitor gradually in general integrated circuit (IC) applications. Besides, the MOM capacitor ideally do not have the leakage issue. Thus, the MOM capacitor can be used instead of MOS capacitor to avoid the gate leakage issue of thin-oxide devices in nanoscale CMOS processes. With the MOM capacitor realized in the power-rail electrostatic discharge (ESD) clamp circuit, the overall leakage is decreased from 828μA to 358nA at 25°C, as compared to the traditional design with MOS capacitor in the test chip fabricated in a 65nm CMOS process.

Mismatch of lateral field metal-oxide-metal capacitors in 180 nm CMOS process

Metal-oxide-metal (MOM) capacitors represent an attractive alternative to metal-insulator-metal (MIM) capacitors in mixed-signal integrated circuits. Since they are made of metal lines, they can be integrated in standard CMOS processes, and tailored over a wide range of sizes. Mismatch data of MOM capacitors, however, is scarce and typically conservative. Presented is the design and the test results of a custom ADC that employs an array of 1024 MOM capacitors sized at 2 fF. Static performance metrics are presented and compared with those for an ADC based on MIM capacitors. Mismatch data is computed from the results.

A 45 GHz CMOS VCO Adopting Digitally Switchable Metal-Oxide-Metal Capacitors

A 45 GHz millimeter-wave (MMW) VCO adopting digitally switchable metal-oxide-metal (MOM) capacitors as the tuning element is described in this work. The MOM capacitor is designed to have discrete capacitance values in order to extend frequency tuning range. The MMW VCO with the switchable MOM capacitor demonstrates an operation frequency ranging from 43.5 to 45.5 GHz. The measured phase noise at 3 MHz offset is less than -97 dBc/Hz across the entire frequency band. The VCO core consumes 4 mW power under a 1 V supply. The measured FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> is -173.

Millimeter-Wave Passives in 45-nm Digital CMOS

With dramatically increased f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> , CMOS technologies have been widely applied in the design of millimeterwave circuits. To reduce the fabrication cost, digital CMOS processes may be used. Due to the lack of thick top metal and the reduced distance between the top metal and silicon substrates in a digital CMOS, the design of high-performance passives becomes very challenging, particularly in the millimeter-wave frequency regime. In this letter, passives with novel structures were fabricated in a 45-nm digital CMOS process. These passives, including transmission lines, spiral inductors, and metal-oxide-metal (MOM) capacitors, were designed and characterized up to 110 GHz. Their performance was compared with those fabricated using 180- and 90-nm RF CMOS processes. These passives achieved good performance in the millimeter-wave regime. A MOM capacitor has a self-resonant frequency higher than 110 GHz. An inductor achieves a quality factor of 24 at 70 GHz. These results show the feasibility of implementing the millimeterwave passives and systems in a 45-nm digital CMOS process.

A 65-nm High-Frequency Low-Noise CMOS-Based RF SoC Technology

The radio-frequency (RF) performance of a 65-nm RF technology is assessed. The RF CMOS was fabricated with a physical gate length of 60 nm. In addition to the deep-n-well and p+-guard-ring isolation, a multi-poly-finger layout and fabrication process is optimized to improve the CMOS device RF performance. A superior cutoff frequency fT of 250 GHz and a maximum oscillation frequency f max of 220 GHz for the n-MOSFETs (NMOS) have been achieved. The minimum noise figures ( NF min's) are around 0.2 and 0.3 dB at 2.4 and 5.8 GHz, respectively. n+/n-well accumulation-mode MOS varactors, inductors, and metal-oxide-metal (MOM) capacitors are integrated with CMOS devices in a single chip by a standard logic process without extra masks. The tuning ratio of the varactor can be up to 12 with a peak quality (Q) factor of 20. The polysilicon-patterned ground shield and 3.7-?m-thick Cu metal process are implemented to improve the Q factor of the inductors. The structure and performance of the MOM and metal-insulator-metal capacitors are benchmarked, and a mesh structure is proposed to reduce the mismatch of the MOM capacitors.

Thermal stabilities of metal bottom electrodes for Ta2O5 metal-oxide-metal capacitor structure

Abstract Thermal stabilities of various metal bottom electrodes were examined by using a Ta 2 O 5 metal-oxide-metal (MOM) capacitor structure. After depositing 10-nm thick Ta 2 O 5 on metal-electrode/poly-Si, we performed rapid thermal oxidation (RTO) at 850 °C for 60 s in an O 2 ambient. A chemical-vapor-deposition (CVD) WSi 2 electrode showed satisfactory thermal stability after the RTO, while other examined electrode materials exhibited thermal degradation caused by oxidation failure or interfacial reaction between the substrate poly-Si and the Ta 2 O 5 . After post-annealing at 650 °C for 30 min (in N 2 condition) with CVD TiN top electrode, an effective oxide thickness ( T ox ) of ∼32 A and a leakage current density of ∼10 7 A/cm 2 at 1.25 V were obtained from the MOM capacitor with the WSi 2 bottom electrode. Other electrode materials, such as TiN, TiSi x , WN x , W, and Ta, were severely oxidized during the RTO in the MOM structures, and very poor capacitor properties were obtained in terms of T ox and leakage current.

Defect dominated charge transport in amorphous Ta2O5 thin films

Ta 2 O 5 is a candidate for use in metal–oxide–metal (MOM) capacitors in several areas of silicon device technology. Understanding and controlling leakage current is critical for successful implementation of this material. We have studied thermal and photoconductive charge transport processes in Ta2O5 MOM capacitors fabricated by anodization, reactive sputtering, and chemical vapor deposition. We find that the results from each of these three methods are similar if one compares films that have the same thickness and electrodes. Two types of leakage current are identified: (a) a transient current that charges the bulk states of the films and (b) a steady state activated process involving electron transport via a defect band. The transient process involves either tunneling conductivity into states near the Fermi energy or ion motion. The steady state process, seen most commonly in films &amp;lt;300 Å thick, is dominated by a large number of defects, ∼1019–1020 cm−3, located near the metal–oxide interfaces. The interior of thick Ta2O5 films has a substantially reduced number of defects. Modest heating (300–400 °C) of Ta2O5 in contact with a reactive metal electrode such as Al, Ti, or Ta results in interfacial reactions and the diffusion of defects across the thickness of the film. These experiments show that successful integration of Ta2O5 into semiconductor processing requires a better understanding of the impact of defects on the electrical characteristics and a better control of the metal–Ta2O5 interface.

Capacitors for Microwave Applications

The properties and design of a metal-oxide-metal (MOM) capacitor are reviewed and its performance is compared with that of conventional MOS and metalized ceramic capacitors. The MOM structure is fabricated by growing a high-performance dielectric such as SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> or Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> on silicon and metalizing the dielectric with several mils of copper, after which the silicon "handle" is removed and replaced with copper. The MOM capacitor has the high capacitance density, low dielectric loss, and low temperature coefficient properties of thermally grown dielectrics. In addition, the resistive electrode loss is minimized by the replacement of the Iossy silicon with copper. The electrode loss for the MOS and MOM capacitors is evaluated as a function of frequency and is in good agreement with the loss estimated from the surface sheet resistance. The series resistance of an MOM capacitor is only 10 percent of that measured for a comparable MOS structure. MOM capacitors have been successfully soldered into circuits; these assemblies have been temperature cycled and high temperature stressed.