Metal-oxide Field-effect Transistors Research Articles

Characteristics of silicon-based polycrystalline diamond MOSFETs prepared by three-step growth method

Hydrogen-terminated diamond (H-diamond) metal oxide field effect transistors (MOSFETs) were successfully fabricated on polished first-grown and unpolished secondary-grown silicon-based polycrystalline diamond films. The devices have a gate length of 8 μm, while an Al2O3 dielectric bilayer was deposited at 200 °C and 100 °C using atomic layer deposition (ALD). Compared to the first-grown diamond films with a root-mean-square roughness (Rq) of 257 nm, the films after polishing and subsequent second growth change the diamond growth mode, resulting in a mixed surface morphology characterized by faceted and step-bunching structures with a roughness (Rq) of 16.6 nm, and also leading to a decrease in grain boundary density and polishing-induced defects. Device analysis demonstrates that these changes result in an increase in the on/off ratio from 102 to 107 at a gate leakage current of 10−7 mA/mm. Meanwhile, although polished first-grown diamond films have atomic-level smoothness, the devices channels on unpolished secondary-grown diamond films show higher carrier concentration and mobility. The improvement in device performance indicates that the three-step growth method provides a new opportunity for the application of large-sized silicon-based polycrystalline diamond films in electronic devices.

Research on anti-single event ability and reinforcement method of SiC MOSFET

Abstract High-voltage silicon carbide (SiC) metal-oxide field-effect transistor (MOSFET) is limited by its ability to resist single event effect (SEE), so it is necessary to study its ability to resist SEE and form an effective reinforcement method. In this paper, it will be studied that how the influence of device structure on the anti-single event ability of SiC MOSFET from the irradiation experiment, and the safe working area of single event leakage degradation of the device is examined. It is found that the width of junction field effect transistor (JFET) and P- type ohmic contact interval both affect the SEE of the device. The SEE mechanism of the device is analyzed based on the experimental results. And the failure caused by local electrothermal stress concentration is confirmed. In view of this mechanism, the reinforced structure is designed with SiO2 barrier layer added in the single event sensitive area, the electrical stress is effectively alleviated, and the peak drain current is reduced by about 18%.

Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

<p>The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.</p>

Assessment of the Biosensing Capabilities of SiGe Heterojunction Negative Capacitance-Vertical Tunnel Field-Effect Transistor.

In this study, a comparison of the negative capacitance vertical tunnel field-effect transistor (NC-VTFET) and VTFET for biosensing applications was conducted. Dielectrically modulated TFET demonstrates better sensitivity than the traditional metal oxide field effect transistor as a biosensor in label-free biosensing applications. The TFET biosensor, however, has much room for advancement by enhancing its DC characteristics. This research addresses the impact of ferroelectric gate oxide for integration of negative capacitance (NC) effect with the SiGe heterojunction pocket at the source-channel junction to enhance performance for biosensor applications. By putting the NC layer over SiO2, the channel voltage increases with decreased subthreshold slope and OFF current, thereby creating an NC effect. Because SiGe has a narrow band gap, pocket doping of SiGe near the source channel junction will increase the concentration of charge carriers, improving the band-to-band tunneling. In order to aid in the integration of biomolecules and to modulate band-to-band tunneling based on charge density (qf), dielectric constant (k), temperature, and cavity length, a cavity is additionally inserted above the source channel junction and underneath the NC layer, near to SiO2. These values were compared with and without the incorporation of NC layer with respect to various electrical properties such as drain current (Id), sensitivity, and electric field (E). According to the findings, labeled and label-free biosensors' sensitivity may be increased by incorporating the NC effect into VTFET biosensors.

Tweaking the Performance of Dielectric Modulated Junctionless Double Gate Metal Oxide Field Effect Transistor-Based Label-Free Biosensor

In this study, we have explored the characteristics of a dielectric-modulated, junctionless (JL) double gate (DG) metal oxide field-effect transistor (MOSFET) featuring a misaligned cavity. Our investigation primarily revolves around proposing optimized device dimensions by examining the influence of varying the height and length of the cavity on the device’s sensitivity. We have delved into the variation of sensitivity parameters, including threshold voltage, ON current, ON-OFF current ratio, and transconductance. Furthermore, our research delves into the effects of both charged and neutral biomolecules on the DC characteristics of the proposed biosensor. We have scrutinized the placement and fill-factor variations of biomolecules within the cavity region, elucidating their impact on sensitivity. Notably, we observed that a 100% filled cavity yields the highest sensitivity. Additionally, this work encompasses a comprehensive exploration of the practical biosensing mechanism tailored for detecting Streptavidin. Based on the ON-OFF current ratio, a maximum selectivity factor of 2.38 (biotarget over bioreceptor) has been observed. Our extensive simulations, conducted using SILVACO ATLAS, rigorously investigate the effects we describe. Altogether, this study highlights the potential of misaligned-cavity JL-DG-MOSFET-based label-free biosensors as cost-effective and simplified analytical tools for biomolecule detection.

Performance improvement of junctionless SOI-MOSFETs by a superior depletion technique

This work uses a superior depletion technique to present a junctionless silicon-on-insulator (SOI) metal-oxide field-effect transistor (MOSFET) in a 14 nm regime. The suggested technique embeds a P-type area into the buried silicon oxide (SiO2) layer. The p-silicon area has several effects on the proposed structure (EPB-JLSM): First, it helps us attain a full depletion area in the channel. Second, the self-heating improves due to the higher thermal conductivity of silicon than the silicon nitride. Finally, the embedded area causes the lower hole concentration (high Vds at accumulation mode), resulting in a better kink effect. Also, we discuss the impact of inserting the P-silicon area geometry into the buried layer on the DC performance device, such as height and thickness. The P-silicon area decreases the leakage current (IOFF) by three orders of magnitude (∼1000%), and also slightly enhances the drive current (ION) (∼20%), and reduces subthreshold swing (SS) from 186 to 109 mV dec−1 (∼71%) compared to a typical junctionless SOI MOSFET (C-JLSM). Furthermore, we discuss the effect of the buried region and gate insulator materials on the proposed device’s performance.

Implementation of Optimized Planar Hall Effect Sensor as Tunable Resistors With DC Bias Control

The emerging requirements of tunable resistors or pseudoresistors for electrical and electronic circuits demand the rigorous attention of engineers in recent times. The frequency-dependent behavior of conventional pseudoresistors operating with gate-controlled metal oxide field effect transistors (FET) creates a subtle challenge to operate in high-frequency applications. Therefore, this letter investigates a tunable resistor with a planar Hall plate to eliminate the frequency-dependent limitations of FETs. The proposed design of a tunable resistor with an optimized Hall effect sensor is able to achieve resistance tuning in the range of 1.8 Ω–247 KΩ. Apart from that, this letter investigates different geometries of planar Hall plate devices and their impact on biasing and magnetic fields that produce a compelling choice for tunable resistors. The proposed scheme exhibits a THD value of 1.4e-8% for a 10-MHz input signal, which is superior to its counterparts based on gate-controlled field effect devices.

Improving total body irradiation with a dedicated couch and 3D-printed patient-specific lung blocks: A feasibility study.

Total body irradiation (TBI) is an important component of the conditioning regimen in patients undergoing hematopoietic stem cell transplants. TBI is used in very few patients and therefore it is generally delivered with standard linear accelerators (LINACs) and not with dedicated devices. Severe pulmonary toxicity is the most common adverse effect after TBI, and patient-specific lead blocks are used to reduce mean lung dose. In this context, online treatment setup is crucial to achieve precise positioning of the lung blocks. Therefore, in this study we aim to report our experience at generating 3D-printed patient-specific lung blocks and coupling a dedicated couch (with an integrated onboard image device) with a modern LINAC for TBI treatment. TBI was planned and delivered (2Gy/fraction given twice a day, over 3 days) to 15 patients. Online images, to be compared with planned digitally reconstructed radiographies, were acquired with the couch-dedicated Electronic Portal Imaging Device (EPID) panel and imported in the iView software using a homemade Graphical User Interface (GUI). In vivo dosimetry, using Metal-Oxide Field-Effect Transistors (MOSFETs), was used to assess the setup reproducibility in both supine and prone positions. 3D printing of lung blocks was feasible for all planned patients using a stereolithography 3D printer with a build volume of 14.5×14.5×17.5 cm3. The number of required pre-TBI EPID-images generally decreases after the first fraction. In patient-specific quality assurance, the difference between measured and calculated dose was generally<2%. The MOSFET measurements reproducibility along each treatment and patient was 2.7%, in average. The TBI technique was successfully implemented, demonstrating that our approach is feasible, flexible, and cost-effective. The use of 3D-printed patient-specific lung blocks have the potential to personalize TBI treatment and to refine the shape of the blocks before delivery, making them extremely versatile.

A compact circuit-level model for single-event burnout in SiC power MOSFET devices

This paper presents a compact circuit-level model for single-event burnout (SEB) in silicon carbide (SiC) metal-oxide field-effect transistors (MOSFETs). Key parameters of the equivalent circuit model of the MOSFET are analyzed and determined in detail, including nonlinear parasitic drain-source capacitance and nonlinear parasitic gate-drain capacitance. The effect of the parasitic bipolar junction transistor is considered and an iteratively optimized double-exponential current source is used to simulate the transient power current generated by incident heavy ions. The equivalent circuit model of the MOSFET is verified by comparing the SPICE simulation curves, TCAD simulation curves, and the curves in the SiC power double trench MOSFET’s datasheet (SCT3080KL). Then, the SEB is caused by heavy ions at various incident positions, linear energy transfer values, drain-source voltage (V ds), and gate-source voltage (V gs) using the TCAD and HSPICE simulations. Simulation results on the SPICE model coincide with the TCAD simulation results. Moreover, this compact model is used to predict the SEB threshold for devices with higher breakdown voltage ratings.

Addressing gain-bandwidth trade-off by a monolithically integrated photovoltaic transistor

The gain-bandwidth trade-off limits the development of high-performance photodetectors; i.e., the mutual restraint between the response speed and gain has intrinsically limited performance optimization of photomultiplication phototransistors and photodiodes. Here, we show that a monolithically integrated photovoltaic transistor can solve this dilemma. In this structure, the photovoltage generated by the superimposed perovskite solar cell, acting as a float gate, is amplified by the underlying metal oxide field-effect transistor. By eliminating deep-trap defects through processing optimization, we achieved devices with a maximum responsivity close to 6 × 104 A/W, a specific detectivity (D*) of 1.06 × 1013 Jones, and an f3dB of 1.2 MHz at a low driving voltage of 3 V. As a result, a record gain-bandwidth product is achieved. The device further exhibits the advantage in photoplethysmography detection with weak illuminations, where our device accurately detects the detailed features that are out of the capability of conventional photodetectors.

Analytical modeling and performance assessment of high performance split-gate dielectric modulated InGaAs GAA junctionless MOSFET biosensor

In this manuscript, split gate dielectric modulated gate-all-around junctionless metal oxide field-effect transistor (SG-GAA-JLFET) based on III-V compound (InGaAs) has recently come forward as a potentiated device in biosensors design due to ultra-sensitivity, selectivity & real-time label-free detection capabilities. In this paper, the boundary conditions at the edges of the junctions are discussed, and their consequences on the Analytical modeling in GAA-JLFET are investigated. The channel-center potential equation is computed by evaluating 2-D Poisson's equation based on the parabolic-potential technique. Additionally, the change of device dimensional parameters upon biosensor sensitivity is computed to investigate the dielectric modulation effects for neutral and charge biomolecules, per se. A SILVACO TCAD simulation tool is utilized for verification and validation of the proposed analytical model. The sensitivity metric of the neutral analyte with a higher dielectric constant is found raised. The value of surface potential sensitivity for Gelatin (k = 12) is seen as 72 which is proportionately 31%, 60%, and 200% greater compared to the sensitivity of apomyoglobin (k = 8), Bacteriophage T7 (k = 6.3), as well as Glucose Oxidase (k = 3.46) for cavity length equal to 20 nm.

Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies

Many applications, such as integrated circuit based digital signal processors (DSPs) and arithmetic logical units (ALUs), rely on adders and subtractors, which are fundamental blocks. Traditional adders and subtractors were created using complementary metal oxide semi-conductor (CMOS) and field effect transistor (FET) technologies, which have increased the number of transistors, path delays, and power consumption. Therefore, this article focuses on the implementation of hybrid adders and subtractors utilizing FinFET and graphene nano-ribbon FET (GnrFET) based nanotechnologies. Initially, a multiplexer logic-based carry output predictable full adder (COPFA) is developed with a fast selection of carry-outputs, which significantly reduces the delays generated in sum estimation. Then, a path selectable reconfigurable hybrid adder (PSRHA) is developed by selecting the high-speed and low-speed carry propagation paths through the COPFA module. Further, a path selectable reconfigurable hybrid subtractor (PSRHS) also developed using two-complement PSRHA addition. Finally, a single architecture for both addition and subtraction are achieved through a joint reconfigurable hybrid adder and subtractor (JRHAS). From the simulations, the COPFA module resulted in a propagation delay (PD) of 7.2792 ns, static power consumption (SPC) of 2.4369nw, and total energy consumption (TEC) of 0.9077 nJ, while the PSRHA module resulted in PD of 2.45317 ns, SPC of 2.55681nw, TEC of 0.0912 nJ. In addition, the PSRHS module resulted in PD as 2.5297 ns, SPC as 2.8428nw, TEC as 0.0662 nJ, and the JRHAS module resulted in PD as 17.178 ns, SPC as 5.4036nw, TEC as 2.0543 nJ. Overall simulations revealed that the proposed COPFA, PSRHA, PSRHS, and JRHAS resulted in optimal performance as compared to conventional methods in terms of power, delay, and energy metrics.

A high-k Cu-doped ZnO film formed via Ga-ion implantation: The acceptor-donor co-doping approach

Dielectric thin films having high permittivity (high-k) and low dielectric loss is essential for developing high performance capacitive devices like metal oxide field effect transistor or thin film transistor. Ga ion implantation performed on Cu-doped ZnO film fabricated by pulsed laser deposition with optimized doping concentrations and post-implantation annealing yielded film having high permittivity and low dielectric loss (ε = 87 and tan δ = 0.17 at the frequency of 1 kHz). Moreover, the permittivity exhibits good stability over a wide range of frequency from 20 Hz to 10 MHz. The high-k film was characterized by detailed dielectric studies, including frequency dependence of permittivity and dielectric loss, complex electrical modulus analysis, impedance spectroscopy and ac conductivity. The enhancement of the permittivity was attributed to the correlated potential barrier hopping of electrons between the neighboring acceptor-donor defect complex states in the band gap created by the co-doping, thus acting as electric dipoles polarizing the film. This work opens up future possibility for ‘dielectric engineering’. The three-dimensional dielectric spatial profile can be controlled via the selective area ion implantation with the depth controlled by the ion implantation energy. • A high-k Ga-Cu co-doped ZnO film formed via pulsed laser deposition and ion implantation method. • Optimized doping concentrations yielded high permittivity and low dielectric loss (ε=87 and tan δ=0.17 at 1 kHz). • Enhancement of permittivity was attributed to the correlated barrier hopping of electrons between neighboring defect complex.

Study of Electrical Performance of Hetero-Dielectric Gate Tunnel Field Effect Transistor (HDG TFET): A Novel Structure for Future Nanotechnology

Although, dynamic power in portable mobile devices can be reduced by reducing power supply VDD on the cost of increased leakage current. Therefore, maintaining low leakage current in the device is serious issue for minimizing overall power consumption of the circuit and improving the battery life. The conventional Metal Oxide Field Effect Transistor (MOSFET) requires at least 60 mV of gate voltage for better current drive at room temperature which is difficult to achieve due to thermal limit. This limitation of gate voltage requirement degrades the performance of the device at lower VDD. Tunnel Field Effect Transistor (TFET) is a potential candidate to replace CMOS in deep-submicron region due to its lower subthreshold slope SS (&lt; 60 mV/decade) at room temperature. Steep switching in TFET can extend the supply voltage scaling with improved energy efficiency for both digital and analog applications. Despite those advantages, TFETs are suffering from lower ON current and larger ambipolar current. To overcome these shortcomings, a new structure, known as Hetero-dielectric gate TFET (HDG TFET), has been proposed in the literature. Since, in the absence of the compact analytical model, it is difficult to understand the electrical behaviour of the HDG TFET device, therefore, the present paper presents an analytical model of transconductance parameter of HDG TFET device. The electrical performance analysis of HDG TFET device reflects that on current can be increased considerably by choosing gate material of higher work function near the source region which also suppresses the ambipolar current. It is also observed that a thinner silicon film and larger drain bias result in larger transconductance value.

Rapid and low-cost, and disposable electrical sensor using an extended gate field-effect transistor for cardiac troponin I detection.

Field effect transistor (FET) biosensor is based on metal oxide field effect transistor that is gated by changes in the surface charges induced the reaction of biomolecules. In most cases of FET biosensor, FET biosensor is not being reused after the reaction; therefore, it is an important concept of investigate the biosensor with simplicity, cheap and reusability. However, the conventional cardiac troponin I (cTnI) sensing technique is inadequate owing to its low sensitivity and high operational time and cost. In this study, we developed a rapid and low-cost, and disposable electrical sensor using an extended gate field-effect transistor (EGFET) to detect cTnI, as a key biomarker for myocardiac infarction. We first investigated pH sensing characteristics according to the pH level, which provided a logarithmically linear sensitivity in the pH sensing buffer solution of approximately 57.9mV/pH. Subsequently, we prepared a cTnI sample and monitored the reaction between cTnI and cTnI antibodies through the changes in the drain current and transfer curves. Our results showed that the EGFET biosensor could successfully detect the cTnI levels as well as the pH with low-cost and rapid detection.

TCAD simulation analysis of vertical parasitic effect induced by pulsed γ- ray in NMOS from 180 nm to 40 nm technology nodes

The parasitic effect inside metal oxide field effect transistor regarded as the basic structure of large scale digital circuits, has long been considered as an important factor affecting the disturbance, upset and latchup of integrated circuits in pulsed γ-ray radiation environment. To investigate the turn-on mechanism of vertical parasitic effect in NMOSFET induced by pulsed γ-ray radiation, the 40 nm, 90 nm and 180 nm NMOSFET device models are constructed by TCAD and the normal electrical characteristics are calibrated. The trend of vertical parasitic triode current gain, the turn-on conditions of vertical parasitic triode and their influence on working state of NMOSFET are obtained. The simulation results are shown below. 1) The disturbance of well potential inside NMOSFET induced by pulsed γ-ray radiation is the main reason for the turn-on of vertical parasitic triode. 2) When vertical parasitic triode is turn-on, the large secondary photocurrent will be generated inside NMOSFET which will affect the working state of the transistor. 3) The current gain of vertical parasitic triode in NMOSFET decreases with the technology node decreasing. The results provide a theoretical basis for studying the transient ionizing radiation effects of electronic devices.

Thermal transport in beta-gallium oxide thin-films using non-gray Boltzmann transport equation

Phonon transport in β-Ga2O3 thin films and metal-oxide field effect transistors (MESFETs) are investigated using non-gray Boltzmann transport equations (BTEs) to decipher the effect of ballistic-diffusive phonon transport. The effects of domain size, and energy dissipation to various phonon modes and subsequent phonon–phonon energy exchange on the thermal transport and temperature distribution is investigated using non-gray BTE. Our analysis deciphered that domain size plays a major role in thermal transport in β-Ga2O3 but energy dissipation to various phonon modes and subsequent phonon–phonon energy exchange does not affect the temperature field significantly. Phonon transport in β-Ga2O3 MESFETs on diamond substrate is investigated using coupled non-gray BTE and Fourier model. It is established that the ballistic effects need to be considered for devices with β-Ga2O3 layer thickness less than 1 μm. A non-gray phonon BTE model should be used near hotspot in the thin β-Ga2O3 layer as the Fourier model may not give accurate temperature distribution. The results from this work will help in understanding the mechanism of phonon transport in the β-Ga2O3 thin films and energy efficient design of its FETs.

P61 - Metal oxide field effect transistors (MOSFETs) versus optically stimulated luminescence detectors (OSLDs) technology in total body irradiation

P61 - Metal oxide field effect transistors (MOSFETs) versus optically stimulated luminescence detectors (OSLDs) technology in total body irradiation

Modelling and optimization of SiC MOSFET switching voltage and current overshoots in a half‐bridge configuration

Due to the high-speed switching, the switching process of a silicon carbide (SiC) metal oxide field effect transistor (MOSFET) in a practical circuit is susceptible to parasitics and exhibits significant current and voltage overshoots. This may subsequently lower the efficiency of the device, degrade the reliability of the system, increase the level of electromagnetic interference and prohibit the full utilization of SiC MOSFETs’ potential. Conventional qualitative analysis is difficult to support enough guidance to deal with the switching overshoots in practice. In order to implement quantitative analysis of the switching overshoots of SiC power electronic circuits, an analytical model of SiC MOSFET switching behaviour in the half-bridge configuration was derived considering all important parasitic parameters, the non-linear characteristics of the parasitic capacitances and the transconductance coefficient of the device. Based on the derived analytical model, the switching voltage and current overshoots under the specific circuit parameter conditions can be quantitatively evaluated without complex system-level modelling. Sensitivity analysis for the voltage and current overshoots during the switching transient was quantified. Moreover, the effect rule of the gate resistance on the voltage overshoot was revealed. In the article, simulation and experimental results validate the analytical model and analysis results.

A Multiple-Trapping-and-Release Transport Based Threshold Voltage Model for Oxide Thin Film Transistors

This article proposes a generic approach for modelling threshold voltage of oxide thin film transistors (TFTs). Threshold voltage has always been ambiguous in TFTs due to the disordered nature of semiconducting thin films, and in operation in accumulation mode. This differs from the situation with metal oxide field-effect transistors (MOSFETs), wherein strong inversion can be specifically defined. The proposed model considers double exponential distribution of deep state and tail state densities in the bandgap with the multiple-trapping-and-release (MTR) transport model. In this surface potential-based approach, pinned surface potential is defined as the surface potential at which free carrier densities exceed deep state carrier density in the deep state-dominated region. The threshold voltage is defined using pinned surface potential and carrier densities obtained at that surface potential. The model is validated using data from fabricated oxide based TFTs with silicon dioxide (SiO2) and other dielectrics. This article develops and reports a systematic approach for fitting an oxide based TFT analytical model with experimental devices, thus ensuring the flexibility needed for compatibility with various devices.