Modelling and optimization of SiC MOSFET switching voltage and current overshoots in a half‐bridge configuration

Abstract

Due to the high-speed switching, the switching process of a silicon carbide (SiC) metal oxide field effect transistor (MOSFET) in a practical circuit is susceptible to parasitics and exhibits significant current and voltage overshoots. This may subsequently lower the efficiency of the device, degrade the reliability of the system, increase the level of electromagnetic interference and prohibit the full utilization of SiC MOSFETs’ potential. Conventional qualitative analysis is difficult to support enough guidance to deal with the switching overshoots in practice. In order to implement quantitative analysis of the switching overshoots of SiC power electronic circuits, an analytical model of SiC MOSFET switching behaviour in the half-bridge configuration was derived considering all important parasitic parameters, the non-linear characteristics of the parasitic capacitances and the transconductance coefficient of the device. Based on the derived analytical model, the switching voltage and current overshoots under the specific circuit parameter conditions can be quantitatively evaluated without complex system-level modelling. Sensitivity analysis for the voltage and current overshoots during the switching transient was quantified. Moreover, the effect rule of the gate resistance on the voltage overshoot was revealed. In the article, simulation and experimental results validate the analytical model and analysis results.