Metal Insulator Semiconductor Tunnel Research Articles

Unveiling Sub-60 mV/decade Subthreshold Swing in The Oxide Local Thinning (OLT) Gated MIS Tunnel Diodes by TCAD Simulations

Metal-insulator-semiconductor (MIS) tunnel diodes (TD) are widely used in the modern integrated circuit, for its ease of fabrication and low cost. Recently, we have reported that the gated MIS TDs can exhibit sub-60 mV/decade subthreshold swing (SS) [1], which can be further reduced by introducing oxide local thinning (OLT) regions. SSs could be as low as 9.7 and 8.4 mV/decade in gated MIS TDs with the OLT regions formed by soft breakdown and photolithography, respectively [2,3]. The reason is unclear and the feasibility of scaling is of interest. In this work, we unveiled the mechanism and designed the scaled devices with ultra-low SS by TCAD simulation.We performed Silvaco TCAD with the 2-D cylindrical structure identical to [2] (Fig. 1). Models of direct tunneling and quantum confinement were included. The OLT region at the center TD is 100 nm. The OLT region at the gate is 400 μm from the inner gate edge, and the width (W GOLT) varies from 100 to 1000 nm.Fig. 2(a) shows the simulated I TD-V G curves of the OLT gated MIS TDs, denoted as TDOLT+GOLT, with different W GOLT, compared to the one without an OLT region at the gate, denoted as TDOLT, and Fig. 2(b) shows the corresponding SS. TDOLT+GOLT turns-on steeply, with SS approaching 10 mV/decade, close to the value observed in [2,3]. The electron densities n e at 2 nm depth in the silicon under different V G are examined for TDOLT and TDOLT+GOLT with W GOLT = 100 nm in Fig. 3(a) and (b) respectively. n e near the inner gate of the latter case increases abruptly from -0.8 to -0.7 V, due to the injection of the extra electrons from the gate OLT region. Fig. 3(c) shows the electron densities at 2 μm inside the gate edge for different devices, following the similar trend with the I TD-V G curves, indicating that the magnitude of the TD current is determined by n e near the gate edge. Fig. 4 shows the mechanism of TD current under different situations. For V G = -1 V, I TD is off and comes from the generation of electrons under the TD. For V G = -0.5 V, I TD is in the stage 1 and comes from the injection of electrons through the gate OLT region. The injection of electrons results in the steep increase of I TD and subsequently the ultra-low SS. For V G = 0.2 V, I TD is in stage 2 and collects the electrons generated in the whole substrate. The rapid increase of n e at the gate edge can be understood in another point of view. Fig. 5 shows the band diagram laterally near the silicon surface. Since n e depends on the difference between the conduction band energy (E C) and the electron quasi-Fermi level (E Fn), when V G increases from -0.8 to -0.7 V, E C is pushed down while E Fn at the gate edge is pulled up due to the injection of electrons through the gate OLT region. Therefore, the device can have SS lower than 60 mV/dec.To test whether the ultra-low SS characteristics can maintain when scaling down, we performed the simulation of the sub-micro device shown in Fig. 6. We find the TD cannot be turned off if we still use substrate thickness t sub = 5 μm (Fig. 7(a)), since the injection of electrons are too strong. However, by reducing t sub, I TD can be turned off and shows superior performance with on-off ratio over 8 orders and SS lower than 60 mV/decade (Fig. 7(b)). Since the electron diffusion current flowing to the substrate of an MIS TD with the substrate much shorter than the diffusion length can be expressed as J n = (qD n n i 2/t sub N A) e qΔΦ n/kT where q, D n, n i, N A, ΔΦ n, k, T are the elementary charge, electron diffusion coefficient, intrinsic carrier concentration, p-type doping concentration, electron quasi-Fermi level splitting, Boltzmann constant, and temperature, respectively, reducing t sub can lead to a stronger diffusion of electrons to the substrate, and there will be fewer electrons flowing to the gate edge (Fig. 8). Therefore, the electron densities can be lower near the gate edge when V G is negative enough, as shown in Fig. 9, leading to the effective turn-off of the TD.REFERENCES[1] Liao, et al., IEEE Trans. on Electron Devices, 62(6), 2061, (2015).[2] Yang, et al., IEEE Trans. Electron Devices, 66(1), 279, (2018).[3] Chiang, et al., IEEE Trans. Electron Devices, 67(4), 1887, (2020).ACKNOWLEDGEMENTThis work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 111-2221-E-002-192-MY3 and NSTC 111-2622-8-002-001. Figure 1

Unveiling Sub-60 mV/decade Subthreshold Swing in The Oxide Local Thinning (OLT) Gated MIS Tunnel Diodes by TCAD Simulations

In this study, we unveil the sub-60 mV/decade subthreshold swing (SS) characteristics observed in the oxide local thinning (OLT) gated p-type metal-insulator-semiconductor (MIS) tunnel diodes (TD) utilizing TCAD simulations. Through our simulations, we successfully replicate the sub-60 mV/decade SS behavior and attribute this remarkable characteristic to the rapid increase in electron density near the gate edge. This phenomenon arises from electron injection through the gate OLT region under a negative gate voltage, leading to a significant elevation in electron density near the gate edge. Armed with this insight, we design scaled devices to assess the feasibility of achieving sub-60 mV/decade SS behavior. By modulating the substrate thickness, we effectively simulate devices with SS lower than 60 mV/decade across a current range spanning 8 orders of magnitude.

Electrically Driven Plasmons in Metal-Insulator-Semiconductor Tunnel Junctions: The Role of Silicon Amorphization.

We investigate electrically driven plasmon (EDP) emission in metal-insulator-semiconductor tunnel junctions. We find that amorphization of the silicon crystal at a narrow region near the junction due to the applied voltage plays a critical role in determining the nature of the emission. Furthermore, we suggest that the change in the properties of the insulating layer above a threshold voltage determines the EDP spatial properties, from being spatially uniform when the device is subjected to low voltages, to a spotty pattern peaking at high voltages. We emphasize the role of the high-energy emission as an unambiguous tool for distinguishing between EDP and radiative recombination of electrons and holes in the semiconductor.

Improved Two States Characteristics in MIS Tunnel Diodes by Oxide Local Thinning Enhanced Transient Current Behavior

The effect of oxide local thinning (OLT) on the increase in current two states in metal–insulator–semiconductor (MIS) tunnel diodes for dynamic memory usage has been demonstrated. Two orders of magnitude improvement in the read current window could be observed. The MIS sample after performing the deep depletion stress (DDS) would soft breakdown (SBD) and could be effectively considered that the oxide was locally thinned. Pulsed voltage program was used to write on fresh MIS (before SBD) and OLT MIS (after SBD). A larger magnitude of transient read current could be observed for OLT MIS, and subsequently the improved current two states characteristics. The read currents of OLT MIS were stable under the endurance test. The transient behavior of a fresh MIS could be understood by the charging and discharging of a capacitor. On the contrary, the tunneling current would be dominated in an OLT MIS. At the same time, since the electron tunneling only concentrated locally, OLT MIS would take longer to recover to the steady-state. The improvement of read current after OLT forming was reproducible, and various write programs were performed for further examination. TCAD simulations demonstrated that the electrons would leak out and the electron density would decrease under larger gate voltage for OLT MIS. This work has shown the potential of OLT MIS for the dynamic memory usage, and the idea of local thinning on the gate oxide might be beneficial for the design of the future dynamic memory.

Transient Current Enhancement in MIS Tunnel Diodes With Lateral Electric Field Induced by Designed High-Low Oxide Layers

In this work, the steady-state and transient behavior of the metal–insulator–semiconductor tunnel diodes with designed high-low (H/L) oxide layers were studied, by performing experiments and TCAD simulations. The H/L oxide layers were formed by thickening the oxide around the gate edge while still in a tunneling-transparent thickness. This could reduce the leakage or tunneling current at reverse bias by decreasing the minority carrier density near the gate edge via the induced lateral electric field caused by H/L oxides. The characteristics of devices with various designed parameters were under investigation to discover the necessary conditions for the tunneling current reduction. Due to the leakage current reduction, the enhancement of transient current was found out, accompanied with enlarged transient capacitance change. Steady-state and transient simulation could help to confirm the observed phenomenon and also illustrated the existence of lateral electron current flow that reduced the minority carrier density near the gate edge at reverse bias. A memory operation using the H/L device was demonstrated. The read current at 120 ms improved more than an order of magnitude in current window with respect to planar. The stable performance under endurance testing made the H/L device a possible future volatile memory application.

Plasmonic gap resonances of electrically excited MIS-AgNR hybrid system

In this paper, a kind of light-emitting tunnel junction composed of three layers of metal–insulator–semiconductor (MIS, Au-Al2O3-Si) is introduced and this structure mainly relies on electron tunneling to excite SPPs. The finite element method is used to calculate the electric field distribution and extinction spectrum of the silver nanorod (AgNR) placed on the metal–insulator–semiconductor tunnel junction (MIS-AgNR). In the simulation, the influence of tunneling current on the strength of SPPs propagating along the metal surface is quantitatively studied by changing the thickness of the insulator layer of the MIS tunnel junction and the bias voltage across it. The AgNR is placed on the tunnel junction, and the gap distance between the gold surface of the MIS structure and the AgNR is changed to qualitatively study the relationship between the extinction characteristics of the AgNR and the gap distance. The study found that the amount of the tunneling current is proportional to the intensity of the SPPs on the metal surface. In the range of 4 nm–20 nm gap distance, the adjustment of the resonance peak position in the 500 nm–700 nm range of the extinction spectrum is realized. As the gap distance increases, the position of the resonant peak in the AgNR extinction spectrum will undergo blue-shift, and at the same time the intensity of the extinction peak will decrease. It is worth noting that the change of the blue-shift displacement is exponentially related to the change of the gap distance.

Enhanced Transient Behavior in MIS(p) Tunnel Diodes by Trench Forming at the Gate Edge

In this article, a new type of metal-insulator-semiconductor (MIS) tunnel diode (TD), trench MIS TD, was investigated. From the current-voltage characteristics, memory retention, and memory endurance measurements, we found that the trench MIS TDs not only have lower reverse bias current, but also show stronger transient current compared to traditional planar structure MIS TDs. For example, in the 1000-cycle memory endurance test, we observed a 25 times larger current window (CW) in trench devices than the CW of planar devices. We attribute the lower reverse bias current to the fewer minority carriers (electrons) in trench MIS TDs, which is supported by the high-frequency capacitance-voltage (C-V) measurement. As for the enhanced transient behavior of trench MIS TDs, we proposed a mechanism based on the understanding of fewer minority carriers in trench devices to explain our observation. Eventually, we examined the effect of different equivalent oxide thicknesses (EOTs) on the CW and found that the trench devices have better CW in a wide EOT range. Because of the enhanced transient behavior leading to better memory CW, trench MIS TDs have the potential to serve as memory devices.

Light Emission in Metal-Semiconductor Tunnel Junctions: Direct Evidence for Electron Heating by Plasmon Decay.

We study metal–insulator–semiconductor tunnel junctions where the metal electrode is a patterned gold layer, the insulator is a thin layer of Al2O3, and the semiconductor is p-type silicon. We observe light emission due to plasmon-assisted inelastic tunneling from the metal to the silicon valence band. The emission cutoff shifts to higher energies with increasing voltage, a clear signature of electrically driven plasmons. The cutoff energy exceeds the applied voltage, and a large fraction of the emission is above the threshold, ℏω > eV. We find that the emission spectrum manifests the Fermi–Dirac distribution of the electrons in the gold electrode. This distribution can be used to determine the effective electron temperature, Te, which is shown to have a linear dependence on the applied voltage. The strong correlation of Te with the plasmon energy serves as evidence that the mechanism for heating the electrons is plasmon decay at the source metal electrode.

Transient Two-State Characteristics in MIS(p) Tunnel Diode with Edge-Thickened Oxide (ETO) Structure

In this work, the transient two-state characteristics of edge thickened oxide (ETO) metal-insulator-semiconductor (MIS) tunnel diodes with various gate electrode areas were studied. The ETO MIS structures were first compared with the planar MIS structures to prove their transient memory potentials and then were simulated by TCAD to find out the mechanism of them. By TCAD simulation, it was focused that there is a lateral electric field built at the boundary of thin and thick oxides in ETO structure. The ETO MIS structures with various gate electrode areas were compared to find out the relation between the gate area and the transient memory performance. ETO MIS structure with proper gate electrode area was suggested for large transient application.

Coupling sensitivity in concentric metal–insulator–semiconductor tunnel diodes by controlling the lateral injection electrons

Coupling sensitivity between two Al–SiO2–pSi metal–insulator–semiconductor tunnel diodes (MISTDs) was examined by sweeping bias voltage on one MISTD and detecting ground current or floating voltage at another nearby MISTD with the substrate being grounded when performing the measurement. A strong coupling phenomenon between two concentric MISTDs was observed in this work. The experiment shows that the coupling sensitivities have a maximum value at a range of about −0.4 V to −0.7 V and turn to minimum at about the flat band voltage (∼−0.9 V) when bias was swept from 0 to −1 V. The simulation result also shows a maximum lateral diffuse current when the MISTD was biased at about −0.7 V and turns to a small value near the flat band voltage. It was speculated that the lateral electron flow due to piled-up injection electrons is the origin of the observed highly sensitive coupling phenomenon. A possible mechanism was proposed to explain the turnaround phenomenon.

Ultra-Low Subthreshold Swing in Gated MIS(p) Tunnel Diodes With Engineered Oxide Local Thinning Layers

In this article, oxide local thinning (OLT) effects on the performance of a gated metal–insulator–semiconductor tunnel diode (MIS TD) with a p-type substrate were demonstrated through the fabrication of well-defined OLT regions at the gate and the drain. Without soft breakdown treatment of the oxide layer as reported before, the designed OLT patterns give rise to such devices to be of particular use. Specifically, sub-60 mV/decade subthreshold swing (SS) in the transfer characteristics was achieved with OLT regions at the device gate, while the operating voltage, as well as SS, could be further reduced with those at the drain. Moreover, by adjusting the number and area of OLT regions that are evenly distributed within the device, SS could be possibly optimized to a much lower value, e.g., 8.4 mV/decade, over three current decades. The enhanced lateral transport efficiency of minority carriers from the gate to the drain, which leads to the ultra-low SS, is attributed to the OLT region as an extra energy source under negative bias with its effectiveness depending on the area and thicknesses of both the relatively thick and thin oxides. The roles of these physical parameters were investigated using 2-D TCAD simulation and evidenced by experimental results.

Improved Low-Voltage Sensing Performance in MIS(p) Tunnel Diodes by Oxide Thickening at the Gate Fringe

The effect of selective-area oxide thickening in metal–insulator–semiconductor (MIS) tunnel structures on their current–voltage characteristics was investigated in this article. Under a low applied voltage ( $> 100\times $ with respect to the device with thin-only oxide, and so was the photocurrent $> 100\times $ larger under an illuminance of 100 lx. With such an improved sensing performance, the ET MIS tunnel diode may find its use in low-cost sensor applications.

Edge-Etched Al2O3 Dielectric as Charge Storage Region in a Coupled MIS Tunnel Diode Sensor

The effects of an Al2O3 dielectric patterned by wet etching in a metal-insulator-semiconductor (MIS) tunnel diode are studied by I-V, C-V and charge storage characteristics in this paper. The behaviors are obviously different from the device without an etched edge. It is suggested that traps are formed at the edge because of the etching process. A circuit model is proposed to explain the effect of the existence of additional traps. With the etched edge as charge storage region, current ratio of programmed and erased states of the tunnel diode sensor is expanded for 165 times and the retention characteristic is much improved. Meanwhile, charge storage characteristic varies with the thickness of the Al2O3 dielectric. Multilevel demonstration is carried out by specified programming process which is not feasible on coupled MIS previously. In addition, relation between the sensing current and stress conditions is examined. A maximum on/off ratio of 105 is achieved. The study of the etched edge is believed to be beneficial for future development in memory cell constructed by MIS TD.

High rectification ratio metal-insulator-semiconductor tunnel diode based on single-layer MoS2

Single-layer MoS2, with its ultimate atomic thickness, has shown promise to scale down transistors for modern integrated circuitry. On the way to implementing two-dimensional (2D) electronic devices, controlled wafer-scale synthesis of single-layer MoS2, single-layer MoS2 metal-oxide-semiconductor field-effect transistors, ohmic contact of single-layer MoS2 for low contact resistance, etc, have been extensively studied. However, the most commonly used two-terminal electronic component, a diode, which conducts current primarily in one direction, has rarely been reported based on single-layer MoS2. Here, a two-terminal high rectification ratio metal-insulator-semiconductor (MIS) tunnel diode was reported based on single-layer MoS2. The In/Au (10/70 nm) electrode via thermal evaporation was used to form a good ohmic contact with the single-layer MoS2. The Si3N4/Pd/Au (5/10/70 nm) electrode via electron beam evaporation was used to form an MIS tunneling structure with the MoS2, showing a current rectification ratio of up to 107 at room temperature. The high current rectification ratio is realized by controlling the quantum tunneling carrier density and the tunneling barrier width. The single-layer MoS2 MIS tunnel diode fabricated via the silicon technology compatible evaporation method has potential application as a fundamental electronic building block for future 2D electronics.

Gate Oxide Local Thinning Mechanism-Induced Sub-60 mV/Decade Subthreshold Swing on Charge-Coupled MIS(p) Tunnel Transistor

The prerequisite of gate oxide local thinning (OLT) effect for subthreshold swing (SS) reduction to sub-60 mV/decade on charge-coupled metal–insulator–semiconductor (MIS) tunnel transistor is specified in this paper. The OLT process is employed by positive voltage stress, which is regarded as an efficient method to create a soft breakdown of oxides. The gate OLT process dramatically reduces the SS of the device, for instance, from the minimum SS of 79.31 to 9.7 mV/decade. Meanwhile, average SS of 28.22 mV/decade for over two current decades is acquired after the gate OLT process. The enhanced efficiency for minority carrier supply under gate oxide is responsible for the amelioration. The physical mechanism is proposed as the OLT spot-induced energy lateral transport and reduction of the energy barrier for minority carrier supply. The mechanism is then clarified by 2-D TCAD simulation. The extremely low SS and its physical insights of gate OLT effect on charge-coupled MIS tunnel transistor are believed beneficial for future developments on low-SS-related devices.

Effect of Oxide Thickness on The Two-State Characteristics in MIS(p) Tunnel Diode with Ultrathin Metal Surrounded Gate

In this work, the transient two-state currents of ultrathin metal surrounded gate (UTMSG) metal-insulator-semiconductor (MIS) tunnel diodes, in which the periphery portion of the gate metal thickness is about 10 nm, with various oxide thicknesses were studied. The electrical characteristics and transient two-state characteristics in the UTMSG MIS and the regular gate metal-insulator-semiconductor (RG MIS) tunnel diodes with various oxide thicknesses were compared and it was found that the UTMSG MIS devices can maintain larger two-state current window within appropriate oxide thicknesses range of 27 Å ∼ 30 Å. The electrical properties of the UTMSG MIS devices are very sensitive to oxide thickness. Also, it was found that the I-V current hysteresis is closely related to the transient two-state characteristics because of the RC delay at edge.

Absence of Evidence for Fixed Charge in Metal–Aluminum Oxide–Silicon Tunnel Diodes

Here, a controlled variation in the fixed charge density (NF) and thickness of aluminum oxide tunnel insulators is reported, and the impact on Schottky barrier height in metal–insulator–semiconductor (MIS) diodes is studied. Analysis of metal–aluminum oxide–silicon capacitor structures indicates a change in NF from +1 × 1012 cm−2 in as‐deposited films to −2 × 1012 cm−2 in annealed films. An analytical model and numerical device physics simulations are used to predict changes in ­based on these changes in NF and alumina thickness. Surprisingly, Mott–Schottky derived values did not follow the trends predicted by these electrostatic models. In fact, there seems to be no discernable effect of NF in diodes with alumina thicknesses below 2 nm, contrary to contactless measurements of the fixed charge of films of similar thickness. The trends are better explained by a dipole model. It is further shown that in as‐deposited MIS diodes, the dipole is a function of alumina layer thickness, whereas in annealed MIS diodes, the dipole and were roughly constant independent of alumina thickness. These data suggest a strategy by which the of MIS tunnel contacts can be controlled and which has implication for the design of electrical contacts.

Theoretical study of piezotronic metal–insulator–semiconductor tunnel devices

Piezotronics has been an emerging concept coupling piezoelectric and semiconducting properties with potential applications in sensors, flexible electronics and nanoelectromechanical systems. Piezoelectric field is created under an applied strain, which controls the carrier generation, transport, separation or recombination processes at the interface or junction of the semiconductor devices. Based on the piezotronic theory, we present a 1D model for the metal–insulator–semiconductor (MIS) tunnel diode based on the piezoelectric semiconductor. Analytical solutions of piezoelectric modulated tunneling are described to reveal the piezotronic effect on the MIS tunnel junction. A numerical simulation of the carrier transport properties is provided for demonstrating the piezotronic effect on MIS tunnel devices.

Light-to-Dark Current Ratio Enhancement on MIS Tunnel Diode Ambient Light Sensor by Oxide Local Thinning Mechanism and Near Power-Free Neighboring Gate

A charge coupled metal insulator semiconductor (MIS) tunnel transistor after self-protective oxide breakdown process was used for ambient light sensing. The drain part of the transistor is an MIS tunnel diode (TD) with ultrathin oxide, which collects the light and dark currents. A surrounding MIS gate with thicker oxide is placed beside the drain at a distance smaller than $1~\mu \text{m}$ by the method of controlling the undercut of wet etching. Under illumination, the transfer curve of the transistor shows a low subthreshold swing smaller than 60 mV/decade due to the aid of photoemission to the double-exponential mechanism controlled subthreshold current. The device after drain breakdown process shows significant enhancement of light-to-dark current ratio comparing to either single MIS TD or the same structure without breakdown. Also, no additional power is included with the added gate voltage because of the low leakage gate structure. Comparing to the case without gate voltage, the maximum light-to-dark current ratio at a suitable gate voltage shows lower power dissipation, which meets the need of low-power requirement in nowadays’ electronic devices.

On/Off Current Ratio Enhancement by Reducing Electrode Separation in Gate-Controlled MIS Tunnel Transistor

Transistor characteristic was observed in a metal-insulator-semiconductor (MIS) tunnel diode with a nearby gate electrode. Both MIS tunnel diode and gate are Al/SiO2/Si(p) structure. We call this structure as gate-controlled MIS tunnel transistor. In this work, the relationship between couple effect and the gap distance was studied. By reducing the gap distance, the couple effect is enhanced and leads to the increase of Ion and decrease of Ioff. Enhancement of the on/off current ratio can also be expected. In short, gap distance plays an important role in the current behavior of a gate-controlled MIS tunnel transistor.