Metal Gate Research Articles

On-Chip Terahertz Spectroscopy for Dual-Gated van der Waals Heterostructures at Cryogenic Temperatures.

Van der Waals heterostructures have emerged as a versatile platform to study correlated and topological electron physics. Spectroscopy experiments in the THz regime are crucial since the energy of THz photons matches that of relevant excitations and charge dynamics. However, their micrometer size and complex (dual-)gated structures have challenged such measurements. Here, we demonstrate on-chip THz spectroscopy on a dual-gated bilayer graphene device at liquid helium temperature. To avoid unwanted THz absorption by metallic gates, we developed a scheme of operation by combining semiconducting gates and optically controlled gating. This allows us to measure the clean THz response of graphene without being affected by the gates. We observed the THz signatures of electric-field-induced bandgap opening at the charge neutrality. We measured Drude conductivities at varied charge densities and extracted key parameters including effective masses and scattering rates. This work paves the way for studying novel emergent phenomena in dual-gated two-dimensional materials.

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Hetero dielectric based dual material gate AlGaN channel MISHEMT for enhanced electrical characteristics

Herein, we report an AlGaN channel metal insulator semiconductor high electron mobility transistor (MISHEMT) in dual material gate (DMG) architecture with two different dielectrics as gate insulator for enhancing the DC performance of the device. The use of a high-k dielectric material as gate insulator below gate metal 1 and a low-k dielectric below gate metal 2 results in significant threshold voltage variation along the channel. This contributes to improved average carrier velocity which in turn results in better current drive. The proposed device exhibits a peak current of 162 mA/mm at zero gate bias, whereas, the DMG and single material gate (SMG) AlGaN channel HEMTs offer currents of 137 mA/mm and 125 mA/mm respectively. The peak transconductances are about 24.66 mS/mm, 23.68 mS/mm and 22.71 mS/mm respectively for the proposed device, DMG and SMG HEMTs. The proposed device reduces the OFF current by an order of 106 compared to that of DMG HEMT.

Low‐temperature SOI SiGe/Si superlattice FinFET with omega‐shaped channel and self‐allied silicide for 3D sequential IC

AbstractIn this letter, to improve the performance and reduce leakage currents of bulk low‐temperature multi‐layer SiGe/Si superlattice (SL) fin field‐effect transistors (FinFETs), a p‐type omega‐shaped channel (Ω‐channel) SL FinFET is realized by etching a Si/Si0.7Ge0.3 triple‐layer stacked structure in a replacement metal gate (RMG) module on a silicon‐on‐insulator (SOI) substrate. In addition, a self‐allied Ni0.9Pt0.1 silicide process and a low‐thermal‐budget (≤400°C) integration procedure were performed on the Ω‐channel SL FinFET. Test results demonstrate that the on‐state current (Ion) is increased by 5.5 times (from 78 to 429 µA/µm) and the off‐state current (Ioff) is reduced by 78.8% (from 5.2 × 10−3 to 1.1 × 10−3 µA/µm) when compared with the corresponding currents of traditional bulk SL FinFETs.

Triple and quadruple metal gate work function engineering to improve the performance of junctionless double surrounding gate In0.53Ga0.47As nanotube MOSFET for the upcoming Sub 3 nm technology node

In line with Moore's Law and the International Roadmap for Devices and Systems (IDRS), shrinking MOSFET dimensions to the 3 nm technology node requires the introduction and thorough investigation of new device structures and advanced materials. The current study focuses on the implementation of Triple Metal (TM) and Quadruple Metal (QM) gate work function engineering techniques on both junctionless (JL) and inversion mode (IM) Double surrounding Gate (DSG) In0.53Ga0.47As nanotube (NT) MOSFET. The objective is to analyze the drain current (ID) characteristics for a gate length of 3 nm using Silvaco ATLAS 3D TCAD. In order to make a fair comparison between JL and IM In0.53Ga0.47As NT, the doping concentration of TM and QM JL In0.53Ga0.47As NT is tuned to achieve two specific objectives. Firstly, the goal is to produce the same ION as IM In0.53Ga0.47As NT. Secondly, the aim is to achieve the same threshold voltage (VTH) as IM In0.53Ga0.47As NT. It was discovered that the IOFF for JL devices is approximately 2.93 times smaller compared to IM devices in the TM situation, while considering matching ION and VTH. The JL devices have an IOFF that is 12.9 times smaller and an IOFF that is 102 times smaller compared to the IM device for the QM situation. This is achieved by matching the ION and VTH values. It achieves a lesser drain-induced barrier lowering (DIBL) of approximately 28.10 mV/V, a virtually perfect subthreshold slope (SS) of roughly 60mV/dec, and a larger current ratio of ION/IOFF, which is approximately 1.42 × 107.

Virtual Fabrication of 14nm Gate Length n-Type Double Gate MOSFET

Due to Moore's law, it is that predicted the channel length of a metal-oxide-semiconductor Field Effect Transistor (MOSFET) will tend to shrink from the submicron to the nanoscale size. Thus, precision in the manufacturing process has become crucial. This study describes the virtual fabrication as well as the electrical characteristics of a 14nm NMOS double gate with a bilayer graphene/high-K/metal gate. In this device, Hafnium Dioxide (HfO2) is employed as a high-k material, and Tungsten Silicide (WSix) is used as a metal gate. Several Silvaco TCAD Tools, including ATHENA and ATLAS, were utilized in the fabrication and simulation of the device, respectively. According to the simulation results, the optimal threshold voltage (VTH), drive current (ION), and leakage current (IOFF) and subthreshold slope (SS) values are 0.2059 V, 797.5650 μA/μm. 29.5794 nA/μm, and 89.1712x10-3 V respectively. The findings of this research showed that the efficiency of this 14nm double gate n-type MOSFET device is satisfactory because the threshold voltage and leakage current parameters are in accordance with ITRS 2013, and that it may have been utilized as a utility man in future modelling and optimization efforts.

WS2 Nanosheet-Based Ultrascaled Field-Effect Transistor for Hydrogen Gas Sensing: Addressing the Sensitivity-Downscaling Trade-Off.

In this paper, we propose an ultrascaled WS2 field-effect transistor equipped with a Pd/Pt sensitive gate for high-performance and low-power hydrogen gas sensing applications. The proposed nanosensor is simulated by self-consistently solving a quantum transport equation with electrostatics at the ballistic limit. The gas sensing principle is based on the gas-induced change in the metal gate work function. The hydrogen gas nanosensor leverages the high sensitivity of two-dimensional WS2 to its sur-rounding electrostatic environment. The computational investigation encompasses the nanosensor's behavior in terms of potential profile, charge density, current spectrum, local density of states (LDOS), transfer characteristics, and sensitivity. Additionally, the downscaling-sensitivity trade-off is analyzed by considering the impact of drain-to-source voltage and the electrostatics parameters on subthreshold performance. The simulation results indicate that the downscaling-sensitivity trade-off can be optimized through enhancements in electrostatics, such as utilizing high-k dielectrics and reducing oxide thickness, as well as applying a low drain-to-source voltage, which also contributes to improved energy efficiency. The proposed nanodevice meets the prerequisites for cutting-edge gas nanosensors, offering high sensing performance, improved scaling capability, low power consumption, and complementary metal-oxide-semiconductor compatibility, making it a compelling candidate for the next generation of ultrascaled FET-based gas nanosensors.

High-Performance Dual-Gate Transistors Based on Aligned Carbon Nanotubes.

Aligned carbon nanotubes (A-CNTs), with atomic-scale thickness and ultrahigh carrier mobility, hold promise for constructing future sub-1 nm node integrated circuits (ICs) with higher speed and lower power consumption. However, the fabricated A-CNT transistors often suffer from the disorder of high-density CNT, which degrade the off-characteristic deviating significantly from theoretical values. Introducing a dual-gate (DG) configuration can provide higher gate control efficiency compared to conventional single-gate (SG) transistors and is expected to enhance the overall performance of A-CNT transistors. However, the reported A-CNT dual-gate field-effect transistors (DG-FETs) still exhibit nonideal switching behavior, and systematic exploration and optimizations for constructing high-performance A-CNT DG structures have been lacking so far. In this work, we conducted a detailed study on the matching issues between the top-gate (TG) and bottom-gate (BG) stacks. By optimizing the gate metal materials and dielectric layer thickness, we enabled 20 nm channel A-CNT DG-FETs to achieve leading switching characteristics, including an on-state current density (Ion) of up to 1.47 mA/μm, a peak transconductance (Gm) of 2 mS/μm, a subthreshold slope (SS) as low as 83 mV/decade, and a current on/off ratio of 106. This study provides critical experimental guidance for constructing outstanding A-CNT DG-FETs at advanced technology nodes to compete with cutting-edge silicon-based chips and is also valid for two-dimensional channels.

Temperature dependence of the low-frequency noise in AlGaN/GaN fin field effect transistors

Low-frequency (LF) noise measurements are compared for Schottky-gate AlGaN/GaN heterostructure planar and fin field-effect transistors (FinFETs) as functions of gate voltage and measuring temperature. The noise of each device type is consistent with a carrier number fluctuation model. Similar effective defect-energy Eo distributions are derived for each of the two device architectures from measurements of excess drain-voltage noise-power spectral density vs temperature from 80 to 380 K. Defect- and/or impurity-related peaks are observed in the inferred energy distributions for Eo < 0.2 eV, Eo ≈ 0.45 eV, and Eo > 0.6 eV. Significant contributions to the LF noise are inferred for nitrogen vacancies and ON and FeGa impurity complexes. Ga dangling bonds at fin interfaces with gate metal are likely candidates for enhanced noise observed in FinFETs, relative to planar devices. Reducing the concentrations of these defects and impurity complexes should reduce the LF noise and enhance the performance, reliability, and radiation tolerance of GaN-based high electron mobility transistors.

Taguchi Method Statistical Analysis on Characterization and Optimization of 18-nm Double Gate MOSFETs

A bi-layer graphene with a multigate structure was intensified and analysed on an 18-nm Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) device to obtain an optimal performance parameter. The device has a gate structure made of Titanium Dioxide (TiO2) that serves as a high-k material and a metal gate made of Tungsten Silicide (WSix). The Silvaco TCAD Software which are ATHENA and ATLAS modules were used to enhance the fabrication process of virtual devices and to verify the electrical properties of a specific device. According to the International Technology Roadmap Semiconductor (ITRS) specifications of 0.179 V ± 12.7% for threshold voltage (VTH) and 20 nA/m for leakage current (ILEAK), the Taguchi L9 orthogonal array strategy was used to improve the device process parameters for optimum VTH and ILEAK. For the NMOS device, the process parameter of VTH Adjust Implant Dose was used as the dominant factor while Source/Drain (S/D) Implant Energy was used as the adjustment factor whereby for PMOS device, S/D Implant Energy was the dominant factor while S/D Implant Tilt was the adjustment factor in order to achieve a robust design through the Taguchi method implementation. The percentage affecting the process parameter is then applied to the results of the signal to noise ratio (SNR) of Nominal-the-best (NTB) for VTH and Smaller-the-better (STB) for ILEAK.

Comparing post-deposition and post-metallization annealing treatments on Al2O3/GaN capacitors for different metal gates

Vertical Metal–Insulator–Semiconductor (MIS) capacitors with an Al2O3 thin film as a gate insulator have been fabricated on homoepitaxial GaN-on-GaN samples. The effect of the annealing treatments on the MIS characteristics has been investigated exploring two different approaches: Post-insulator-Deposition-Annealing (PDA) and Post-gate-Metallization-Annealing (PMA), i.e., annealing on the bare Al2O3 layer and annealing after the gate metallization deposition on Al2O3. The direct comparison between PDA and PMA is crucial to understand the impact of the metal/dielectric interface quality on the behavior of the Al2O3/GaN MIS capacitors. The efficacy of annealing has been monitored as a function of metal gates having different work functions: nickel (Ni), molybdenum (Mo), and tantalum (Ta). It has been found that both PDA and PMA approaches are equally able to improve the Al2O3/GaN interface electrical quality. However, the PMA demonstrates an additional beneficial effect on the metal/Al2O3 interface. In particular, the possible chemical reactions activated by the annealing process at the metal/dielectric interface can perturb the known metal/dielectric dipole responsible for Fermi-level pinning phenomena, causing a positive shift of the flat voltage (VFB), which depends on the metal, and approaching the theoretical value in the case of Mo and Ta.

Enhanced Threshold Voltage and Improved Subthreshold Swing Using NiOX/ITO Reverse Bias Gated Diamond pMOS

An increase in the device performance of diamond‐based p‐type metal–oxide–semiconductor (pMOS) transistors using a combination of p‐type nickel oxide and n‐type indium tin oxide (NiOX/ITO) reverse bias diode as the gate dielectric is reported. Negative threshold voltage pMOS transistors are desirable for digital circuits and power applications for fail‐safe operation. A Schottky gate‐based conventional diamond pMOS transistor suffers from many limitations, including a positive threshold voltage (VT). Herein, it is experimentally demonstrated that NiOX/ITO gate dielectric with Al gate contact circumvents many critical limitations, providing a negative threshold voltage of −1.2 V, improved subthreshold slope of 145 mV dec−1, current ON/OFF ratio >107, and peak gate leakage current reduction >103. An Al/NiOX‐based control gate structure shifts the VTH negative with improvements in crucial device performances. Adding a reverse bias junction through the Al/ITO/NiOX heterointerface with the Al metal gate further improves performance. The measured device characteristics are explained in a common framework of energy band diagram for all the devices.

Numerical simulation of core shell dual metal gate stack junctionless accumulation mode nanowire FET (CS-DM-GS-JAMNWFET) for low power digital applications

In this paper, Core Shell Dual Metal Gate Stack Junctionless Accumulation Mode Nanowire FET (CS-DM-GS-JAMNWFET) is proposed, which has enhanced performance and is suitable for analog and digital applications. A high-k gate stack engineering, Hafnium Oxide (HfO2) is deployed in the outer as well as inner gate oxides of the core shell structure. The proposed device is compared with CS-DM-JAMNWFET, CS-SM-JAMNWFET, DM-GS-JAMNWFET, DM-JAMNWFET, and SM-JAMNWFET by maintaining a constant threshold voltage for all structures. The proposed CS-DM-GS-JAMNWFET provides a substantial reduction in subthreshold current with a high Ion/Ioff ratio as compared to other competent device structures. Also, the proposed device exhibits improvements in various parameters compared to the SM-JAMNWFET. It shows improvement in drain current (2.27 times), output conductance (2.14 times), subthreshold swing (0.94 times), transconductance (2.47 times), gate capacitance (2.00 times), cut-off frequency (1.24 times), intrinsic gain (12.95 times), current gain (1.46), Ion/Ioff ratio (6.15 times), unilateral power gain (1.09 times), maximum transducer power gain (1.08 times), Transconductance Generation factor (1.08 times), gain frequency product (14.61 times), transconductance frequency product (1.32 times), and gain transconductance frequency product (17.27 times). These benefits are due to combined advantages of the dual metal high-k dielectric HfO2 structure in core shell JAM FET, which enhances the device's gate dominance over the channel with high driving current.

Impact of SiGe pocket on different shape TFET structures for gas sensing application

Gas sensing requires highly sensitive and selective sensor technologies for environmental monitoring, industrial safety, and public health objectives. Although conventional MOSFET-based gas sensors are widely utilized, their detection of low quantities of gases, such as ammonia, is hindered by a number of severe constraints. TFET is emerged as the better device than MOSFET, particularly for the sensing applications. In this work we discussed the source engineered and shape engineered techniques to improve the performance of TFETs, specifically for ammonia gas detection. Comprehensive simulations on SILVACO TCAD and compared the four TFET structures SiGe-pocket DGTFET, SiGe-pocket vertical TFET SiGe-pocket Z-shape TFET, and SiGe-pocket U-shape TFET structure on the basis of various electrical characterization parameters. Significant improvements in efficiency and sensitivity are obtained by adjusting the work function of the molybdenum (4.40–4.60 eV) catalytic gate metal to find the optimal values. The findings reveal that the SiGe-pocket U-shape TFET structure exhibits superior performance, demonstrating an ION of 8.01 × 10−4 A/μm, an ION/IOFF ratio of 1.25×1013, and an OFF current sensitivity (SOFF) of 1.262. These results highlight the enhanced sensitivity and efficacy of the proposed SiGe-pocket U-shape tunnel FET in ammonia gas sensing applications, making it a promising candidate for practical uses in environmental monitoring and industrial safety.

Nonhalogen Dry Etching of Metal Carbide TiAlC by Low-Pressure N2/H2 Plasma at Room Temperature.

Ternary metal carbide TiAlC has been proposed as a metal gate material in logic semiconductor devices. It is a hard-to-etch material due to the low volatility of the etch byproducts. Here, a simple, highly controllable, and dry etching method for TiAlC has been first presented using nonhalogen N2/H2 plasmas at low pressure (several Pa) and 20 °C. A capacitively coupled plasma etcher was used to generate N2/H2 plasmas containing active species, such as N, NH, and H to modify the metal carbide surface. The etch rate of TiAlC was obtained at 3 nm/min by using the N2/H2 plasma, whereas no etching occurred with pure N2 plasma or pure H2 plasma under the same conditions. The surface roughness of the TiAlC film etched by N2/H2 plasma was controlled at the atomic level. A smooth etched surface was achieved with a root-mean-square roughness of 0.40 nm, comparable to the initial roughness of 0.44 nm. The plasma properties of the N2/H2 plasmas were diagnosed by using a high-resolution optical emission spectrometer, detecting the NH molecular line at 336 nm. The etching behavior and plasma-surface reaction between N2/H2 plasma and TiAlC were investigated by using in situ spectroscopic ellipsometry, in situ attenuated total reflectance-Fourier transform infrared spectrometry, and X-ray photoelectron spectroscopy. The findings indicate that the N-H, C-N, and Ti(Al)-N bonds form on the TiAlC surface etched by the N2/H2 plasmas. The mechanism for etching of TiAlC involving transformation reactions between inorganic materials (metal carbides) and inorganic etchants (N2/H2 plasma) to form volatile organic compounds such as methylated, methyl-aminated, and aminated metals is proposed. Nonhalogen or nonorganic compound etchants were used during the etching process. The study provides useful insights into microfabrication for large-scale integrated circuits.

Enhanced breakdown voltage for p-GaN gate AlGaN/GaN HEMT on AlN/Si with triple trenches: A simulation study

This study presents an analysis of an AlGaN/GaN high-electron-mobility transistor (HEMT) with a triple-trench structure (TT-HEMT) for the enhancement of breakdown voltage, which is often limited by the high electric field near the gate edge. Using COMSOL Multiphysics, simulations were run, with trenches made of gallium nitride (GaN) constructed between the GaN and aluminum nitride (AlN) nucleation layers. Each trench was positioned directly beneath the source, gate, and drain contacts. Under the metal gate, a p-type doped GaN cap is added to produce an enhancement mode device, which is more desirable in high-power applications. The results indicate that the effective dispersion of the electric field distribution enhances the breakdown voltage of the device by 70 % in comparison to a conventional HEMT. Additionally, the impact of various design parameters, such as the p-GaN doping concentration and the metal gate work function on the electrical performance, was also investigated. Overall, the proposed device structure exhibits superior electrical properties for high-power applications.

Nanoscale Trench Gate Engineered JAM Gate-All-Around (TGE-JAM-GAA) Label-Free BioFET for Charged/Neutral Biomolecules Detection

In this manuscript, a Trench Gate Engineered Junctionless Accumulation Mode Gate-All-Around (TGE-JAM-GAA) BioFET structure has been proposed and critically analyzed for the label-free identification of biomolecules using extensive numerical device simulations. This device is superior in terms of a variety of performance metrics, including higher sensitivity, a larger shift in threshold voltage, drain current, transconductance, and the ION/IOFF current ratio. These improvements are due to both the triple metal gate engineering and the trench gate. A comparative analysis of TGE-JAM-GAA BioFET has been performed with a triple metal normal gate JAM Gate-All-Around FET (TMNG-JAM-GAAFET) and a conventional single metal normal gate JAM Gate-All-Around FET (SMNG-JAM-GAAFET) biosensor. For instance, in the case of APTES biomolecules, the drift in threshold voltage obtained is 236.24 mV, which is 58.75% and 159.18% higher than that of the TMNG-JAM-GAAFET and SMNG-JAM-GAAFET, respectively, demonstrating that the TGE-JAM-GAA BioFET is more suitable for applications in biosensing.

Two-dimensional-materials-based transistors using hexagonal boron nitride dielectrics and metal gate electrodes with high cohesive energy

Two-dimensional-materials-based transistors using hexagonal boron nitride dielectrics and metal gate electrodes with high cohesive energy

Design of Monolithically Integrated Temperature Sensors in 4H-SiC JFETs

In this paper we study and compare two designs of a temperature sensor monolithically integrated to a vertical SiC JFET. One sensor utilizes the standard JFET P+ aluminum gate implantation scheme. The advantage of this sensor is that the integration with a JFET process flow can be achieved with no additional process steps or mask layers. The other sensor uses a combination P-body and a low energy P+ implantation scheme, typically seen in MOSFETs. Both sensors exploit the variation of resistance with temperature of Al doped SiC. Drift-Diffusion simulations of both designs are carried out at fixed temperatures, exhibiting an excellent ~53% relative reduction in sensor resistance from 300 to 450K. However, neither design shows linear behavior with temperature, beginning to saturate at 450K. Electrothermal simulations are also deployed to verify the sensor robustness as the sensor is locate relatively far from the JFET junction. Due to the high thermal conductivity of SiC, the sensor average temperature follows closely the junction temperature. Current crowding (or 2D effects) close to the contact edges is observed in both sensors. We also deploy a simple analytical model to calculate the resistance as a function of the temperature for both sensors. The model agrees with the drift-diffusion calculations, however due to the 2D nature of current flow, a maximum 19.6% relative error is obtained. In general, both sensors deployed similar relative sensitivity, however the P-body sensor resistance changes in a range of 10.6kΩ to 4.95kΩ compared to 700Ω to 330Ω for the P+ sensor.

Temperature Characterization and Performance Enhancement of a 7nm FinFET Structure Using HK Materials and GaAs as Metal Gate (MG)

Temperature Characterization and Performance Enhancement of a 7nm FinFET Structure Using HK Materials and GaAs as Metal Gate (MG)