Metal Gate FinFET Research Articles

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Scallop-shaped p-type FinFETs with improved short-channel effects immunity and driving current

In this work, scallop-shaped p-type fin field-effect transistors (S-FinFETs) that outperform control-FinFETs for a given gate length are fabricated based on a conventional high-к metal gate FinFET fabrication flow. Because of the scallop-shaped gate structure and ultra-thin (∼5 nm) S-fin channel, the S-FinFETs demonstrate a 25% improvement in subthreshold swing and a 54% decrease in drain-induced barrier lowering compared with those of the control-FinFETs for a 20 nm physical gate length. Furthermore, a driving current of 200 μA/μm is obtained for S-FinFETs with a source/drain epitaxial substrate and a gate length of 20 nm, matching the performance of control-FinFETs with a source/drain epitaxial substrate. With improved short-channel effect immunity, the proposed S-FinFET provides a promising candidate beyond-FinFET technology.

A 16-kb Antifuse One-Time-Programmable Memory in 5-nm High-K Metal-Gate FinFET CMOS Featuring Bootstrap High-Voltage Scheme, Read Endpoint Detection, and Pseudodifferential Sensing

This letter presents a 16-kb antifuse macro in a 5-nm high-K, metal-gate FinFET CMOS for the first time. Bootstrap high-voltage scheme (BHVS), read endpoint detection (REPD), and pseudodifferential sensing (PDS) are proposed to lower intrinsic bit error rate (BER) below 1 ppm for in-field programming and achieve ten years of data retention at 125 °C.

Quantum Dot With a Diamond-Shaped Channel MOSFET on a Bulk Si Substrate

In this article, a p-type high- ${k}$ /metal gate (HKMG) FinFET with a special diamond-shaped channel on a bulk Si substrate for the formation of gate-induced quantum dot (QD) is reported. The electrical characteristics of the device at various temperatures and bias voltages for QD formation are extensively investigated. Remarkable oscillations in the drain current are observed for the 30-nm gate length ( ${L}_{g}$ ) transistor at ${T} =20$ K. By analyzing the experimental results as well as the simulation data obtained by TCAD, it is found that the carriers are strongly localized at the small sharp tip of the channel and the thick spacers contribute to a large confinement potential for forming QD with a large charging energy of 30 meV. This provides a promising approach for large-scale QD fabrication and integration using the mainstream bulk complementary metal oxide semiconductor (CMOS) process.

Improvement in electrostatic effeciency using workfunction modulated dual metal gate FinFET

This paper demonstrates a 3-D simulation study of a workfunction modulated dual material gate FinFET (WMDMGF). The source side gate material workfunction of a dual material gate FinFET is modulated linearly keeping drain side material workfunction to be constant. This model provides improvement in terms of DC performance such as better drive current and minimum threshold voltage. Thus, enhancing the switching characteristics of the device and providing better speed. The model is simulated using Silvaco TCAD tool, and the results are compared with single metal gate and dual metal gate FinFET performance.

Subthreshold Performance Improvement of Underlapped FinFET Using Workfunction Modulated Dual-metal Gate Technique

Workfunction modulated dual material gate FinFET (WMDMG-FinFET) is proposed to improve the DC performance of the device. A dual metal gate FinFET with linear modulation in workfunction along the source side of gate electrode keeping drain side gate electrode workfunction to be constant is introduced. Its subthreshold performance (i.e., switching ratio and subthreshold swing) is enhanced by introducing spacers in the side-walls of gate, with underlap concept. SILVACO TCAD tool is used to carry out the simulation work. The simulation results are compared for different spacers and it is observed that TiO2 spacer with high-k dielectric gives the best switching ratio and lowest subthreshold swing. The WMDMG-FinFET with spacers in the underlapped region shows better subthreshold characteristics as compared to conventional DMG-FinFET.

Electron Beam Inspection in Physical Mode: Overpolish Monitoring of RMG CMP

For a recent replacement metal gate (RMG) FINFET technology using an SOI substrate, an inhomogeneous polish post Tungsten fill of the RMG was discovered. For particular wide-gate structures, the Tungsten polish within the reticle field and across the wafer varied widely despite being in control using the established kerf metrology structure. This was discovered after the technology had been ramped to production. An in-line monitor was needed but could not be dependent on kerf structures to monitor within-reticle variation, since these monitored only narrow-gate within-wafer and wafer-to-wafer variation. So, a within reticle inspection using Electron Beam Inspection (EBI) was used to characterize the within-reticle and within-wafer variation of the wide-gate structures.

Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability

Fin height and width dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high- $\kappa $ metal gate (HKMG) FinFET transistors is reported for the first time. It was observed that NBTI degradation is less severe when increasing the physical height of the silicon fin. The increased fin height results in a lower effective defect density, believed to be related to a reduced role of the defective fin corners and/or top surface. In addition, activation energies for the capture process in tall fins during NBTI stress show lower values while charge trapping in standard height fins is highly temperature dependent. PBTI results reveal a similar, albeit less severe, impact of fin height, suggesting an impact of fin height on the high- $\kappa $ layer, with again an increased defectivity at the fin corners and/or top surface, whose effective role is reduced in the case of taller fin. On the other hand, PBTI shows limited temperature dependence, independent of fin height.

FinFET With Improved Subthreshold Swing and Drain Current Using 3-nm Ferroelectric Hf0.5Zr0.5O2

High-performance negative capacitance p-type FinFETs (p-FinFETs) with a 3-nm-thick ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer are fabricated based on a conventional high- ${\kappa }$ metal gate FinFETs fabrication flow. The devices show improved subthreshold swing values [34.5 mV/dec for 500-nm gate length (LG) and 53 mV/dec for 20-nm-LG devices] and slight hysteresis voltages (~9 mV for $\textsf {L}_{\textsf {G}} = \textsf {500}$ nm and ~40 mV for $\textsf {L}_{\textsf {G}} = \textsf {20}$ -nm transistors). With the integrated FE film, a strong driving current enhancement (up to 260%) is also obtained compared with that of conventional FinFETs. The inherent reasons for the improved characteristics contribute to the low-interface state density ( ${D}_{\sf it}$ ) and the perfect channel electrostatic integrity.

Novel GAA Si Nanowire p-MOSFETs With Excellent Short-Channel Effect Immunity via an Advanced Forming Process

In this letter, Gate-All-Around (GAA) nanowire (NW) p-MOSFETs with new approaches to fabricate totally isolated channels in replacement metal gate (RMG) are reported for the first time. Few reformed fin forming processes based on conventional high- k /metal gate FinFET flow are implemented to fabricate the GAA devices. Two profiles of NW channels, such as circular and inverted droplet, were fabricated by H2 baking and oxidation methods in the RMG process. The proposed methods would increase the process thermal budget and improve film quality for the NW channels. Providing both structural and process advantages, the optimized devices with $L_{g} = 16$ nm demonstrate superb short-channel effect (SCE) immunity characteristics, with SS = 61.86$ mV/dec and DIBL = 6.5 mV/V for the inverted droplet NW device; these results are very close to the ideal limits of MOSFETs. The results also indicate that the inverted droplet NW devices have a slightly better SCE control than the circular NWs of similar geometric size.

Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices

Electronic devices consume a large amount of energy globally, and this is projected to accelerate in the near future with greater societal connectivity and cloud storage. To meet power saving goals, both the DC leakage power ( $\text{P}_{\mathrm{ DC}}$ ) and switching AC power ( $\text{P}_{\mathrm{ AC}}$ ) consumption of future electronics must be lowered. Electronic materials play a central role for ultra-low power electronics. To lower the transistor’s gate and source-drain leakage current, high- $\kappa $ dielectric plus metal gate technologies and FinFET structures have been implemented in CMOS. The scaling of supply voltage ( $\text{V}_{\mathrm{ DD}}$ ) is an effective way to lower $\text{P}_{\mathrm{ AC}}$ , where the transistor’s current degradation can be compensated by using high mobility channel materials, such as p-channel Ge, and n-channel InGaAs; high-mobility metal-oxide semiconductors, or two-dimensional (2D) materials. The ultimate $\text{V}_{\mathrm{ DD}}$ reduction is limited by the transistor’s turn-on slope. One proposed solution is the Tunnel FET, where carriers are injected by band-to-band-tunneling directly to the channel. Another method to reach <60 mV/dec turn-on slope is to integrate piezoelectric or ferroelectric materials into MOSFETs. These new electronic materials can also be used for ultra-low power memory application beyond existing DRAM thereby enabling technology for processor-in-memory and brain mimicking chips.

Effect of Gate-Line-End-Induced Stress and Its Impact on Device’s Characteristics in FinFETs

The gate-line-end (GLE)-induced stress effects on the high- $k$ /metal-gate FinFETs was investigated. Compared with the devices with the GLE of 35 nm, those with the GLE of 100 nm presented 6.3% and 5.7% enhancement in drive current for the n- and p-FinFETs, respectively. It was attributed to the effective transverse-tensile-stress transfer from gate to the Si-fin channel. Furthermore, as the fin numbers increased from 1 to 10, the degradation in the saturation current of the devices with the GLE of 100 nm, resulting from the neighboring gates, relaxed the transverse tensile strain in the channel to 3.9% and 3.6% for n- and p-FinFETs, respectively.

(Invited) Variability in FinFET SRAM Cells

Recently, variability of the devices due to the various random sources is increasing and will reduce the yield of the circuit. To overcome these problems, FinFET device technologies have been proposed and investigated for many years. They have an intrinsic strength against the SCE and they allow the use of intrinsic channel and thus reduce the random dopant fluctuation. However, variability of the FinFET still remains. Variations are caused by fluctuations of the gate-length (ΔLG), the fin-width (ΔTFin), the oxide thickness (ΔTox), the line edge roughness of fin and gate electrodes. In addition to these variations, a new source of variation is generated through an introduction of the metal gate (MG) due to the dependency of the work function (WF) on the orientation of metal grains. To understand the origin of the Vth variation in the MG FinFET, we experimentally evaluate the effect of the ΔLG, ΔTFin, and ΔTox to the Vth variation by measuring the standard deviation of these values. The standard deviations of the dimension variation sources such as the ΔLG and ΔTFin were measured by counting the statistical distribution of the size using a scanning electron microscope (SEM). The same chip is used after the electrical measurements. The ΔTox variation was measured by ellipsometry using (110) oriented test wafers which have the same orientation with the side-wall channel of the FinFET. It is revealed that the ΔLG, ΔTFin, and ΔTox contributions to the Vth variation are insignificant since their standard deviations and partial derivatives are small. Thus, it is concluded that the main variation source of the TiN MG FinFET is the work function variation (WFV) of the TiN. The observed deviation of 30 mV is almost the same value with the previous reports. The possible explanation of the WFV is an over 200 mV work function difference between (100) and (111) oriented grains of TiN and there is also an additional WFV due to the composition or nitrogen concentration of the TiN. Moreover, we have developed and introduced amorphous metal gate into FinFET for the first time using the TaSiN metal gate to overcome the work function variation in the metal gate. The TaSiN gates exhibit smaller variability than that of TiN and the record smallest variability is realized. The Vth variation will directly cause the variation in the SRAM performance. To overcome the variation problem, we have developed independent doubl-gate (IDG) FinFET SRAM technologies. We have developped two types of FinFET SRAM cells using the IDG-FinFET. One is a flexible-Vth (Flex-Vth) SRAM cell and the other is a flexible pass-gate (Flex-PG) SRAM cell. In the Flex-Vth cell, all the transistors in the cell are composed by the IDG-FinFET. The Vth of the all transistor can be controlled by the external bias to the Vth-control-gate. The real values of Vth can be tuned keeping the symmetry of Vth. Thus, the stand-by leakage current and the short circuit current of the cell are dynamically controlled. For the Flex-PG cell, IDG-FinFETs are used only for the PG and the other transistors are composed by the common-DG FinFET. The Ion ratio of the pull down to the pass gate which corresponds to the β-ratio is thus flexibly changed. A great enhancement of the read margin is experimentally confirmed for the Flex-PG cell. Moreover, significant reduction of the variation in the SRAM characteristics is clearly demonstrated. Finally, scalability of the Flex-PG SRAM technology is evaluated by the compact model analysis. Device parameters including variations are satisfactory to the ITRS roadmap. The result shows that the TaSiN gate and the Flex-PG technology enable 12.5-nm-LG SRAM with the sufficient static noise margin.

A 16 nm 128 Mb SRAM in High-&lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;$\kappa$&lt;/tex&gt;&lt;/formula&gt; Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications

FinFET technology has become a mainstream technology solution for post-20nm CMOS technology [1], since it has superior short-channel effects, better sub-threshold slope and reduced random dopant fluctuation. Therefore, it is expected to achieve better performance with lower SRAM VDDMIN. However, the quantized sizing of the channel width and length has drawbacks for conventional 6T-SRAM bitcell scaling. To minimize the bitcell area of the high-density SRAM bitcell, the number of fins (setting the channel width, W) of the pull-up PMOS (PU), passgate NMOS (PG) and pull-down NMOS (PD) transistors must be selected as 1:1:1. Since PU, PG, and PD have the same channel length (L), the ratio in geometry between the PU transistor and the PG transistor is equal to one. With the process variations, the strength of PU transistor can be much stronger than the PG transistor. A stronger PU transistor increases read stability of the SRAM bitcell but it degrades the write margin significantly and results in worse write-VDDMIN issue. Figure 13.5.1(a) shows a contention condition between PU and PG transistors of a 6T-SRAM bitcell for the write operation. During the write operation, the PU transistor impedes the ability of the PG transistor to pull the storage node (S) from VDD to ground. The bitcell may suffer a write failure at the stronger PU with weaker PG condition caused by the device variations. Two techniques have been proposed to improve the high density SRAM bitcell write VDDMIN: 1) negative bit-line voltage (NBL) to increase the strength of PG transistor and 2) lower cell VDD (LCV) to weaken PU transistor strength [1-5]. Compared to the conventional techniques, this work develops a suppressed-coupling-signal negative bitline (SCS-NBL) scheme and a write-recovery-enhancement lower-cell-VDD (WRE-LCV) scheme for write assist without the concern of reliability at higher VDD operating region. A comparison of the effectiveness of the two design techniques is also performed. Figure 13.5.1(b) shows the layout view of the high-density 6T-SRAM bit-cell with 0.07μm2 area in a 16nm high-k metal-gate FinFET technology. To minimize area, we set the geometric ratio of PU, PG, and PD transistors all equal to one. With the two developed write-assist circuits, the overall VDDMIN improvement can be over 300mV in a 128Mb SRAM test-chip.

Technological development of high-k dielectric FinFETs for liquid environment

This work presents the technological development and characterization of n-channel fully depleted high-k dielectric FinFETs (Fin Field Effect Transistor) for applications in a liquid environment. Herein, we provide a systematic approach based on Finite Element Analysis for a high-control fabrication process of vertical Si-fins on bulk and we provide many useful fabrication expedients. Metal gate FinFETs have been successfully electrically characterized, showing excellent subthreshold slope SS=72mV/dec and high Ion/Ioff≈106 ratio, with power consumption of the order of tens of nW. The FinFETs have also been proved to correctly behave in a liquid environment. We also present the HfO2 characterization towards full pH response sensing applications.

Suppression of threshold voltage variability of double-gate fin field-effect transistors using amorphous metal gate with uniform work function

An amorphous TaSiN metal gate (MG) is introduced into double-gate fin field-effect transistors (FinFETs) to suppress work function variation (WFV) of the MG, which is a dominant source of threshold voltage (Vt) variability for MG FinFETs. Comparing with a poly-crystalline TiN gate, the TaSiN gate reduces Vt variation dramatically and thus records the smallest AVt value of 1.34 mV μm reported so far for the MG-FinFETs. By decomposing the variation source due to interface trap density, the WFV suppression using the amorphous MG is confirmed to be effective to achieve the well-suppressed variability of the MG-FinFETs.

Investigation of Strain Engineering in FinFETs Comprising Experimental Analysis and Numerical Simulations

This study combines direct measurements of strain, electrical mobility measurements, and a rigorous modeling approach to provide insights about strain-induced mobility enhancement in FinFETs and guidelines for device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel holographic technique. A large vertical compressive strain is observed in metal gate FinFETs, and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFET lateral interfaces with respect to (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of stress components in the fin width, height, and length directions on the mobility of both n- and p-type FinFETs and to identify optimal stress configurations. Finally, self-consistent Monte Carlo simulations are used to investigate how the most favorable stress configurations can improve the on current of nanoscale MOSFETs.

FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics

This paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull down n-channel FETs with fin line-edge roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading READ static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite,0 and Vtrip variations, hence degrade the variability of WRITE SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-fe metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread,0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the μ/σ ratio in RSNM.

(Invited) Advanced FinFET Technologies: Extension Doping, Vth Controllable CMOS Inverters and SRAM

The advanced FinFET technologies including extension doping, threshold voltage controllable CMOS inverters and the b-ratio optimized SRAMs are presented. It is experimentally found that the best extension ion implantation conditions are dose of 4x1014 cm-2 and tilted angle of 60o. With further increasing dose, the device performance deteriorates owing to the incomplete recrystallization of amorphous regions in the thin extensions. The logic gate threshold voltage controllable single metal gate FinFET CMOS inverter constructed by a tied-gate 3-terminal (3T) PMOS and an independent double-gate 4-terminal (4T) NMOS is proposed and demonstrated. Furthermore, the FinFET SRAMs with different b-ratios were fabricated and evaluated. The higher b-ratio provides the large static noise margin at read condition due to the high current drivability of pull-down transistor.

Implications of fin width scaling on variability and reliability of high-k metal gate FinFETs

In this paper, we report a study to understand the fin width dependence on performance, variability and reliability of n-type and p-type triple-gate fin field effect transistors (FinFETs) with high-k dielectric and metal gate. Our results indicate that with decreasing fin width the well-known performance improvement in terms of sub-threshold swing and drain-induced barrier lowering are accompanied by a degradation of the variability and the reliability. As a matter of fact fin width scaling causes (i) higher hot-carrier degradation (HC) in nFinFETs owing to the higher charge carrier temperature for the same internal stress voltages; (ii) worse negative bias temperature instability (NBTI) in pFinFETs due to the increased contribution from the (1 1 0) surface; (iii) higher variability due to the non-uniform fin extension doping, as highlighted by applying a novel characterization technique.