Metal-ferroelectric-semiconductor Research Articles

Structural, ferroelectric and dielectric properties of Na0.5Bi0.5(Ti0.98Fe0.02)O3 thin films on different substrates

Na0.5Bi0.5(Ti0.98Fe0.02)O3 (NBTFe) thin films have been prepared on monocrystalline Si, Al-doped ZnO/glass and Pt/TiO2/SiO2/Si substrates by metal organic decomposition combined with sequential layer annealing. The structure, leakage current, ferroelectric and dielectric properties of NBTFe thin films are very sensitive to the using substrates. The NBTFe on Si exhibits a competitive growth mode with various oriented crystallites at different annealing temperature. At 550 °C, the NBTFe on all the substrates crystallize into the pure rhombohedral perovskite structure with an obvious difference in orientation. The electrical measurements were conducted on metal–ferroelectric–semiconductor and metal–ferroelectric–metal capacitors. The NBTFe film on Si exhibits the capacitance–voltage curve with a maximum memory window of 2 V at the applied voltage of ±6 V originated from the ferroelectric polarization. The NBTFe film on Al-doped ZnO/glass shows a round polarization–electric field hysteresis loop due to the large contribution from the leakage current. In contrast, a large remanent polarization (Pr) of 18 μC/cm2 for NBTFe deposited on Pt/TiO2/SiO2/Si can be obtained. Also, the NBTFe thin film on Pt/TiO2/SiO2/Si shows a high er of 313 and low tan δ of 0.1 at 100 kHz.

Thickness dependent charge transport in ferroelectric BaTiO3 heterojunctions

We have investigated the effect of ferroelectric barium titanate (BaTiO3) film thickness on the charge transport mechanism in pulsed laser deposited epitaxial metal–ferroelectric semiconductor junctions. The current (I)–voltage (V) measurements across the junctions comprising of 20–500 nm thick BaTiO3 and conducting bottom electrode (Nb: SrTiO3 substrate or La2/3Ca1/3MnO3 buffer layer) demonstrate the space charge limited conduction. Further analysis indicates a reduction in the ratio of free to trapped carriers with increasing thickness in spite of decreasing trap density. Such behaviour arises the deepening of the shallow trap levels (<0.65 eV) below conduction band with increasing thickness. Moreover, the observed hysteresis in I–V curves implies a bipolar resistive switching behaviour, which can be explained in terms of charge trapping and de-trapping process.

Tuning the resistive switching memory in a metal–ferroelectric–semiconductor capacitor by field effect structure

Resistive switching (RS) effects based on a correlation between ferroelectric polarization and conductivity might become of particular interest for nonvolatile memory applications, because they are not subjected to the scaling restrictions. Here we report on RS behaviors modulated by a reversal of ferroelectric polarization in heterostructures comprising of a ferroelectric layer and a semiconducting manganite film. It is found that electrically conducting state is bistable or even tristable; and via the polarization flipping, a maximum resistive switching coefficient (Rmax/Rmin) is found to be larger than 3000 with bias of 6V in Ag/BaTiO3/La0.8Ca0.2MnO3 at room temperature. More importantly, employing field-effect structure with ferroelectric PMN-PT as substrate, we found that the resistive switching behaviors can be tuned in situ by modulating the concentration of carriers in the semiconducting manganite layer. Possible mechanisms are discussed on the basis of the interplay of bound ferroelectric charges, charged defects in ferroelectric layer and mobile carriers in manganite thin films. The giant RS effects observed here may be of significance for memory devices by combing electronic conduction with magnetic, spintronic, and optical functionalities.

The effects of Bi4Ti3O12 interfacial ferroelectric layer on the dielectric properties of Au/n-Si structures

Au/n-Si metal-semiconductor (MS) and Au/Bi4Ti3O12/n-Si metal-ferroelectric-semiconductor (MFS) structures were fabricated and admittance measurements were held between 5 kHz and 1 MHz at room temperature so that dielectric properties of these structures could be investigated. The ferroelectric interfacial layer Bi4Ti3O12 decreased the polarization voltage by providing permanent dipoles at metal/semiconductor interface. Depending on different mechanisms, dispersion behavior was observed in dielectric constant, dielectric loss and loss tangent versus bias voltage plots of both MS and MFS structures. The real and imaginary parts of complex modulus of MFS structure take smaller values than those of MS structure, because permanent dipoles in ferroelectric layer cause a large spontaneous polarization mechanism. While the dispersion in AC conductivity versus frequency plots of MS structure was observed at high frequencies, for MFS structure it was observed at lower frequencies.

Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Study of the Capacitive Properties of Strontium Barium Niobate Deposited by Radio Frequency Magnetron Sputtering

Ferroelectric SrxBa1−xNb2O6 (SBN) thin films are deposited on Al/Si (100) substrates by radio frequency magnetron sputtering at room temperature. The nanograin sizes of the SBN thin films were analized by scanning electron microscopy (SEM). X-ray diffraction reveals that all the SBN thin films show an amorphous structure because they were deposited at room temperature.The capacitive properties of the SBN thin films were measured using metal ferroelectric insulation semiconductor (MFIS) structures. The memory window of the MFIS structure was characterized with a capacitance-voltage (C-V) method.

Fabrication of Poly(Vinylidene Fluoride/Trifluorothylene) Thin Films on Si Substrates Using Polyvinyl Alcohol Buffer Layers

The characteristics of a metal–ferroelectric–insulator–semiconductor structure were investigated using poly(vinylidene fluoride/trifluorethylene)(65/35) as a ferroelectric layer and polyvinyl alcohol as an insulating buffer layer. It was found in the metal–insulator–semiconductor structure that the polyvinyl alcohol obtained from 0.4 wt.% solution gave excellent insulator results with a bias sweep range of ± 5 V. The leakage current densities of the polyvinyl alcohol films obtained from 0.1, 0.4 and 0.7 wt.% solutions amounted to 10−5 A/cm2, 10−6 A/cm2 and 10−7 A/cm2, respectively. Based on these results, the 0.4 wt.% polyvinyl alcohol solution was selected for use in the metal–ferroelectric–insulator–semiconductor structures. The width of the memory window in the metal–ferroelectric–semiconductor and metal–ferroelectric–insulator–semiconductor structures measured at a voltage sweep of ±5 V was 2 V and 3 V respectively, whereas the respective current densities amounted to 10−5 and 10−6 A/cm2 at 5V.

A Model of Ferroelectric Field-Effect Transistor after Ionizing Radiation

A theoretical model for radiation effect in a metal-ferroelectric-semiconductor (MFS) field-effect transistor was proposed by considering the fixed charges (Qfx) and interface charges (Qit) induced by ionizing radiation. In this model, the energy band-bending and surface charge in Si at a given gate bias were calculated systematically as a function of fixed charges (Qfx) and interface charges (Qit). The drain-source current (ID) was derived in an exact form without any approximation. All modeling done in this work was generalized to both n and p type Si substrates with an easy sign of the Fermi level potential in the formalism. The derived results demonstrate that the symmetry of polarization versus gate voltage curve of the MFS structure degrades when Qfx and Qit increase, which can explain the imprint behavior successfully. Additionally, the residual polarization in the ferroelectric field-effect transistor decreases with increasing Qfx and Qit, which can account for the polarization reduction. As expected, the calculated transfer characteristic of the ferroelectric FET shows that the subthreshold voltage is significantly affected by Qfx and Qit. This investigation may provide some useful insights for the space applications of ferroelectric FET’s.

Electrical characterization of the metal ferroelectric oxide semiconductor and metal ferroelectric nitride semiconductor gate stacks for ferroelectric field effect transistors

This paper presents our work on electrical characterization of metal-ferroelectric-oxide-semiconductor (MFeOS) and metal-ferroelectric-nitride-semiconductor (MFeNS) structures for nonvolatile memory applications. Thin films of lead zirconate titanate (PZT: 35:65) have been used as ferroelectric material on 2.5–5 nm thick thermally grown SiO2 and Si3N4 as buffer layer for MFeOS and MFeNS structures, respectively. Capacitance-Voltage (C-V) and Current-Voltage (I-V) characteristics were used for electrical characterization. Our comparative results reveal that the MFeNS structure with 2.5 nm thick buffer layer has higher memory window of about 3.6 V as compared to 3 V for similar MFeOS structure. Also superior electrical properties such as lower leakage current and higher dielectric strength were observed in MFeNS structures. Higher nitridation time was observed to deteriorate the polarization characteristics resulting in reduced memory window. The highest memory window of 6.5 V was observed for SiO2 buffer layer thickness of 5 nm. We also observed that the annealing temperature influences the leakage current characteristic and memory window of these structures.

The Ferroelectric Field Effect Transistor Simulation and Analysis

A ferroelectric field effect transistor (FFET) with the metal/ferroelectric/ semiconductor (MFS) structure is designed and simulated. The simulation results show that the drain current at Vg=0 after polarized is decided by Pr and Pr/Ps. When increasing Pr, Id enhanced. When Pr/Ps decreases, Idincreases if the FFET is saturated. When a voltage (Vp=1.5v) is applied on the FFET, Id may be stable and not sensitive to the variation of Pr/Ps. This FFET stable output voltage is decided by Ec.

Electrical Properties of SbSI/Sb_2S_3 Single and Double Heterostructures

The SbSI/Sb2S3 single heterostructures as well as Sb2S3/SbSI/Sb2S3 and SbSI/Sb2S3/SbSI double heterostructures have been produced by applying CO2 laser treatment of p-type SbSI single crystals. The current voltage and transient characteristics of these heterostructures have been measured in temperatures below and above the SbSI single crystal Curie temperature (Tc = 293 K). The results have been tted with appropriate theoretical formulae to determine the following types of the investigated heterojunctions: P p SbSI/Sb2S3, p P p Sb2S3/ SbSI/Sb2S3 and P p P SbSI/Sb2S3/SbSI. In uence of the illumination on electrical properties of SbSI/Sb2S3 single and double heterostructures has been reported. Fabricated new structures may be potentially applicable in electronics and optoelectronics as a new type of metal ferroelectric semiconductor devices.

Analyses of temperature-dependent interface states, series resistances, and AC electrical conductivities of Al/p—Si and Al/Bi4Ti3O12/p—Si structures by using the admittance spectroscopy method

In this study, Al/p—Si and Al/Bi4Ti3O12/p—Si structures are fabricated and their interface states (Nss), the values of series resistance (Rs), and AC electrical conductivity (σac) are obtained each as a function of temperature using admittance spectroscopy method which includes capacitance—voltage (C—V) and conductance—voltage (G—V) measurements. In addition, the effect of interfacial Bi4Ti3O12 (BTO) layer on the performance of the structure is investigated. The voltage-dependent profiles of Nss and Rs are obtained from the high-low frequency capacitance method and the Nicollian method, respectively. Experimental results show that Nss and Rs, as strong functions of temperature and applied bias voltage, each exhibit a peak, whose position shifts towards the reverse bias region, in the depletion region. Such a peak behavior is attributed to the particular distribution of Nss and the reordering and restructuring of Nss under the effect of temperature. The values of activation energy (Ea), obtained from the slope of the Arrhenius plot, of both structures are obtained to be bias voltage-independent, and the Ea of the metal-ferroelectric-semiconductor (MFS) structure is found to be half that of the metal—semiconductor (MS) structure. Furthermore, other main electrical parameters, such as carrier concentration of acceptor atoms (NA), built-in potential (Vbi), Fermi energy (EF), image force barrier lowering (Δ Φb), and barrier height (Φb), are extracted using reverse bias C−2—V characteristics as a function of temperature.

Electrical characterization of MFeOS gate stacks for ferroelectric FETs

We investigated the electrical characterization of metal–ferroelectric–oxide semiconductor (MFeOS) structures for nonvolatile memory applications. Al/PZT/Si and Al/PZT/SiO2/Si capacitors were fabricated using lead zirconate titanate (PZT; 35:65) as the ferroelectric layer. The maximum C–V memory window was 6V for metal–ferroelectric semiconductor (MFeS) structures and 2.95 and 6.25V for MFeOS capacitors with a buffer layer of 2.5 and 5nm, respectively. Comparative data reveal a higher dielectric strength and lower leakage characteristic for an MFeOS structure with a 5-nm SiO2 buffer layer compared to an MFeS structure. We also observed that the leakage characteristic was influenced by the annealing conditions.

Fabrication and Electrical Characteristics of Metal-Ferroelectric Ba(Zr0.1Ti0.9)O3 Film–Insulator-Silicon Structure

We investigated that Al/Ba(Zr0.1Ti0.9)O3 (BZT)/insulator-Silicon metal-ferroelectric-semiconductor (MFIS) and Al/BZT/Pt/Ti/SiO2/Silicon metal-ferroelectric-metal-insu- lator-semiconductor (MFMIS) ferroelectric structures and investigated the memory effect and dielectric constant with different insulator materials of thin films in the MFIS and MFMIS. The BZT thin films on SiO2/Si substrates show good capacitance-voltage characteristics and the threshold voltage shift of 20 V at applied ±30 V bias. However, the leakage current density of BZT on SiO2/Si at 0.5 MV/cm is two orders of magnitude lower than that on SixNy. The clockwise hysteresis loops in C-V curves of the MFIS structure were also observed clearly. From the dependence of C-V properties on different insulator materials, it is deduced that hysteresis loop dominated by the ion vacancy, defect and trap charges in the SixNy films.

Simulation of electrical characteristics in negative capacitance surrounding-gate ferroelectric field-effect transistors

The electrical characteristics of surrounding-gate (SG) metal-ferroelectric-semiconductor (MFS) field-effect transistors (FETs) were theoretically investigated by considering the ferroelectric negative capacitance (NC) effect. The derived results demonstrated that the NC-SG-MFS-FET displays superior electrical properties compared with that of the traditional SG-MIS-FET, in terms of better electrostatic control of the gate electrode over the channel, smaller subthreshold swing (S < 60 mV/dec), and bigger value of ION. It is expected that this investigation may provide some insight into the design and performance improvement for the fast switching and low power dissipation applications of ferroelectric FETs.

The impact of the Pb(Zr,Ti)O3-ZnO interface quality on the hysteretic properties of a metal-ferroelectric-semiconductor structure

The hysteretic properties of metal-ferroelectric-semiconductor (MFS) structures based on Pb(Zr0.2Ti0.8)O3 (PZT) and ZnO films were studied with respect of the quality of the PZT-ZnO interface. The films were grown by pulsed laser deposition (PLD) on platinized silicon (Pt/Si) substrate and on single crystal, (001) oriented SrTiO3 (STO) substrates. The structural analysis has revealed that the PZT-ZnO stack grown on single crystal STO is epitaxial, while the structure grown on Pt/Si has columnar texture. The temperature change of the capacitance-voltage (C-V) hysteresis direction, from clockwise at low temperatures to counter clockwise at high temperatures, was observed at around 300 K in the case of the MFS structure grown by PLD on Pt/Si substrate. This temperature is lower than the one reported for the case of the PZT-ZnO structure grown by sol-gel on Pt/Si substrate (Pintilie et al., Appl. Phys. Lett. 96, 012903 (2010)). In the fully epitaxial structures the C-V hysteresis is counter clockwise even at 100 K. These findings strongly points out that the quality of the PZT-ZnO interface is essential for having a C-V hysteresis of ferroelectric nature, with negligible influence from the part of the interface states and with a memory window of about 5 V at room temperature.

Polarization and interface charge coupling in ferroelectric/AlGaN/GaN heterostructure

Asymmetrical shift behaviors of capacitance-voltage (C-V) curve with opposite direction are observed in two AlGaN/GaN metal-ferroelectric-semiconductor (MFS) heterostructures with Pb(Zr,Ti)O3 and LiNbO3 gate dielectrics. By incorporating the switchable polar nature of the ferroelectric into a self-consistent calculation, the coupling effect between the ferroelectric and the interface charges is disclosed. The opposite initial orientation of ferroelectric dipoles determined by the interface charges is essentially responsible for the different C-V characteristics. A critical fixed charge density of −1.27 × 1013 cm−2 is obtained, which plays a key role in the dependence of the C-V characteristic on the ferroelectric polarization. The results pave the way for design of memory devices based on MFS structure with heteropolar interface.

Orientation growth and electrical properties of ZnO/BaTiO3 heterostructures on silicon substrates by chemical solution deposition

Metal–ferroelectric–semiconductor (MFS) structures based on ZnO/BaTiO3 were fabricated by chemical solution deposition (CSD). The microstructure of the heterostructures was characterized by x-ray diffraction and atomic force microscopy. Both ZnO and BaTiO3 layers were found to be c-axial oriented on LaNiO3-coated silicon substrates. The morphology revealed good interface quality with root-mean-square values of about 10 nm. Compared with BaTiO3 ferroelectric thin films, the capacitance–voltage curves of Pt/ZnO/BaTiO3/LaNiO3 heterostructures exhibited a counterclockwise hysteresis loop for the MFS capacitor confirming the ferroelectric nature integrated with an n-type semiconductor. The memory windows increased and then reduced as the frequency changed from 100 kHz to 1 MHz, which can be explained by a frequency-dependent coercive field and electron injection behaviour. The current–voltage curves of ZnO/BaTiO3 heterostructure showed a good insulating characteristic. These results suggested that ZnO/BaTiO3 MFS heterostructures by CSD can be used for memory devices.

Temperature induced change in the hysteretic behavior of the capacitance-voltage characteristics of Pt–ZnO–Pb(Zr0.2Ti0.8)O3–Pt heterostructures

Pt – ZnO – Pb ( Zr 0.2 Ti 0.8 ) O 3 – Pt (PZT-ZnO) heterostructures were fabricated by using a sol-gel process. Capacitance-voltage measurements performed on a wide temperature range (20–450 K) have revealed the presence of a hysteresis that undergo a change of direction from clockwise at temperatures below 350 K to counter-clockwise at higher temperatures. In the first case, the hysteresis is produced by charge injection, similar to the case of classical metal-oxide-semiconductor capacitors. In the last case, the hysteresis is the fingerprint of polarization reversal, as reported for metal-ferroelectric-semiconductor (MFS) structures based on n-Si. The memory window at 450 K is about 6 V. This result suggests that PZT-ZnO MFS heterostructures can be used for memory devices working at elevated temperatures, in which the ZnO plays the role of the semiconductor.

Structural and electrical properties of K0.5Bi0.5TiO3 thin films for ferroelectric field effect transistor applications

K0.5Bi0.5TiO3 (KBT) thin films have been prepared on p-Si (1 0 0) and Pt/TiO2/SiO2/Si substrates using a metalorganic decomposition method. X-ray patterns show that well-crystallized KBT perovskite thin films have been formed and AFM images reveal that the grain sizes are almost the same (170 nm) on the two substrates. The electrical measurements were conducted on metal–ferroelectric–semiconductor (MFS) or metal–ferroelectric–metal (MFM) capacitors. Both MFS and MFM structures exhibit good insulating properties. The clockwise capacitance–voltage (C–V) hysteresis loops of the MFS structure increase symmetrically due to the ferroelectric polarization of the KBT films when the sweeping voltage is no higher than ±8 V. It is noted that the maximum memory window is as high as 3.1 V. Moreover, an interfacial layer is calculated to be 3 nm formed at KBT/Si. However, as the voltage exceeds ±8 V, the initiated trapped charges cause the memory property to deteriorate. Furthermore, the relaxation behaviour of the KBT films can also be found with the Curie temperature at around 350 °C by the change in the capacitance with temperature.