Electrical characterization of the metal ferroelectric oxide semiconductor and metal ferroelectric nitride semiconductor gate stacks for ferroelectric field effect transistors

Abstract

This paper presents our work on electrical characterization of metal-ferroelectric-oxide-semiconductor (MFeOS) and metal-ferroelectric-nitride-semiconductor (MFeNS) structures for nonvolatile memory applications. Thin films of lead zirconate titanate (PZT: 35:65) have been used as ferroelectric material on 2.5–5 nm thick thermally grown SiO2 and Si3N4 as buffer layer for MFeOS and MFeNS structures, respectively. Capacitance-Voltage (C-V) and Current-Voltage (I-V) characteristics were used for electrical characterization. Our comparative results reveal that the MFeNS structure with 2.5 nm thick buffer layer has higher memory window of about 3.6 V as compared to 3 V for similar MFeOS structure. Also superior electrical properties such as lower leakage current and higher dielectric strength were observed in MFeNS structures. Higher nitridation time was observed to deteriorate the polarization characteristics resulting in reduced memory window. The highest memory window of 6.5 V was observed for SiO2 buffer layer thickness of 5 nm. We also observed that the annealing temperature influences the leakage current characteristic and memory window of these structures.