Metal-ferroelectric-insulator-semiconductor Research Articles

Ferroelectric field effect transistors: Progress and perspective

Ferroelectric field effect transistors (FeFETs) have attracted attention as next-generation devices as they can serve as a synaptic device for neuromorphic implementation and a one-transistor (1T) for achieving high integration. Since the discovery of hafnium–zirconium oxide (HZO) with high ferroelectricity (even at a thickness of several nanometers) that can be fabricated by a complementary metal–oxide–semiconductor-compatible process, FeFETs have emerged as devices with great potential. In this article, the basic principles of the FeFET and the design strategies for state-of-the-art FeFETs will be discussed. FeFETs using Pb(ZrxTi1−x)O3, polyvinylidene fluoride, HZO, and two-dimensional materials are emphasized. FeFETs, ferroelectric semiconductor field effect transistors, and metal–ferroelectric–insulator–semiconductor structures to which those materials can be applied are introduced, and their exotic performances are investigated. Finally, the limitations of these devices’ current performance and the potential of these materials are presented.

Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling

CMOS scaling is the approach to accomplish the VLSI goals in the past decades. The existing CMOS technology is facing challenges related to short channel effects and reached to its performance limits at sub-10 nm technology nodes. The negative capacitance field-effect transistor is a potential device for near future technology to overcome these challenges. In the present work, negative capacitance Junctionless (NC-JL) FinFET with Metal-Ferroelectric–Insulator-Semiconductor (MFIS) structure is proposed and analysed comprehensively using TCAD simulation for its scaling capability over the various technology nodes starting from 24 nm to 5 nm. It is revealed that the integration of negative capacitance (NC) with JL FinFET helps to reduce the leakage current, short channel effects such as subthreshold slope, DIBL and provide high drive current as well as fast switching by reducing intrinsic delay for extremely short channel length as compared to standard-JL FinFET. Furthermore, the different performance parameters including Gate Induced Drain Leakage Current (GIDL) of proposed NC-JL FinFET are comprehensively studied.

CMOS-Compatible Fabrication of Low-Power Ferroelectric Tunnel Junction for Neural Network Applications

A low-cost fabrication process of Hf <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{1}-{x}}$ </tex-math></inline-formula> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) nonvolatile memory (NVM) was proposed and its characteristics were investigated. We successfully fabricated a ferroelectric tunnel junction (FTJ) device with tunable conductance for neural network applications. The proposed FTJ device exhibits excellent performances, such as large conductance ratio of ~40 for a 500-ns pulse and thus satisfied low-power consumption of write pulse (1 fJ per bit) and fast write speed (<500 ns) requirements. Furthermore, we revealed that the metal–ferroelectric–insulator–semiconductor structure had a higher tunneling electroresistance ratio than the metal–ferroelectric–insulator–metal structure. Moreover, the polarization operation of our FTJ devices achieved low-power analog-like conductance transition, multilevel operation, and even endurance characteristics is promising. These results demonstrate that the FTJ has high potential to be an ideal emerging memory for neuromorphic computing. Therefore, HZO-based devices are promising materials in neural network applications for next-generation devices.

Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> ) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ferroelectric/metal/insulator/semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over >6 decades. In a CMOS circuit, due to CCM, low- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> pairs provide steeper subthreshold swing (SS) than high- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> pairs. Transient power/performance is also modeled, and it is shown that a DC-optimal NCFET design, employing broad junctions, CCM, and a low- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.

Ultrathin Sub-5-nm Hf₁₋ₓZrₓO₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate

This study investigates a device’s ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-<i>x</i></sub> Zr <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> O2 (HZO). A conventional field-effect transistor (FET) with pure hafnium (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) is used as a control measure and the impact of an internal metal gate (IMG) is also discussed. The study was conducted by using a sub-5-nm HZO and seed layer to fabricate a gate-all-around (GAA) nanowire (NW); a FeFET with a metal-ferroelectric–metal-insulator-semiconductor (MFMIS) structure; and a double layer (DL) of the channel. The channel size used in the experiment was approximately <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.6\times16$ </tex-math></inline-formula> nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the total thickness of the gate stack was 9.2 nm. This thickness is 50.5% less than our previous experiment. The FeFET exhibits a considerably high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{on}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{off}$ </tex-math></inline-formula> ratio exceeding 107. The IMG serves as a potential equalizer and the ferroelectric material is arranged in a more symmetrical electric field. This results in a lower subthreshold (sub- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{TH}$ </tex-math></inline-formula> ) swing ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S.S._{min}=$ </tex-math></inline-formula> 49.3mV/decade) with a wide range ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{3}$ </tex-math></inline-formula> ) of drain currentcompared to that without an IMG. The findings indicate that a high-performance GAA FET can be achieved by combining a DL channel, GAA NW, ferroelectric material, and an IMG.

Conduction Mechanisms of Metal-Ferroelectric- Insulator-Semiconductor Tunnel Junction on N- and P-Type Semiconductor

Conduction mechanisms of ferroelectric tunnel junction (FTJ) using metal-ferroelectric-insulator- semiconductor (MFIS) on n- and p-type semiconductor is clarified by a new developed model, which is verified by the experimental results. In the model, electron tunneling from conduction band and valence band, and hole tunneling from valence band are included to calculate the read current in ON/OFF-state of MFIS-FTJ. The model explains the unexpected polarization polarity of ON/OFF-state in p-type and the difference of tunneling electroresistance (TER) ratio between n- and p-type MFIS-FTJ, which cannot be understood just by the depletion/accumulation for majority carriers in semiconductor.

Computational Investigation of Negative Capacitance Coaxially Gated Carbon Nanotube Field-Effect Transistors

In this article, we present a computational investigation on nanoscale coaxial-gate negativecapacitance carbon nanotube field-effect transistor (NC CNTFET). The proposed nanodevice is endowed with metal- ferroelectric-metal-insulator-semiconductor (MFMIS) structure. The simulation approach is based on solving self-consistently the nonequilibrium Green's function formalism with the NC FET electrostatics considering ballistic transport conditions. The computational assessment includes the switching performance and shortchannel effects (SCEs) in NC CNTFETs. The negative capacitance behavior of the ferroelectric has been found efficient in boosting the performance of nanoscaleCNTFETs in terms of subthreshold swing (SS), drain-induced barrier lowering (DIBL), ON-current, current ratio, and intrinsic delay. In addition, we show the capability of MFMIS configuration in improving the current ratio and SS of CNTFETs with ultrascaled gate lengths. The role of the ferroelectric layer thickness in enhancing the NC CNTFET performance is also studied, where improved performance has been recorded using thicker ferroelectric layer. Achieving high ION/IOFF current ratio, sub-kT SS, and improved immunity against SCEs makes the NC CNTFET as a potential candidate for modern CNT-based nanoelectronics.

Exploration of Negative Capacitance in Gate-All-Around Si Nanosheet Transistors

Gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) are the most promising candidates to replace FinFETs and nanowire (NW) FETs in future technology nodes owing to their improved short-channeleffects, high current drivability per layout footprint (LF), and extreme scalability. The much-needed voltage scaling in these aggressively scaled devices can be provided by introducing negative capacitance (NC) effect, which results in sub-60 mV/decade switching behavior. In this article, we explore how NC effect manifests into silicon NS transistors by using technology computer aided designs (TCAD). The NC effect originates from a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) configuration in the gate-stack. The performance of single channel NC-NSFET is benchmarked against NC-NWFET and NC-FinFET of comparable device dimensions. NC-NSFET shows 9% and 38% lower subthreshold swing when compared to NC-NWFET and NC-FinFET, respectively. For NC-NSFETs, capacitance matching, between the ferroelectric (FE) and the underlying MOS capacitance, is achieved with a thinner FE layer. Between single stack and double stack devices, single stack NC-NSFET offers faster switching at low operating voltages. Within a stack, nonuniformity in NS cross sections is found to influence device behavior. We also report the performance of NC-NSFETs in terms of key device design parameters, like channel length, thickness, and width of NS, and metal work function (WF), where, thinner NSs and metals with high WF provide significant enhancement in I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio. The results presented here can aid in the design, operation, and performance improvement of emerging NC-NSFET devices.

Lanthanum-doped BiFeO3/ZrO2 gate stack for ferroelectric field effect transistors

A metal–ferroelectric–insulator–semiconductor (MFIS) structure was fabricated with lanthanum (La)-doped BiFeO3 as ferroelectric and ZrO2 as the high-k insulator layer. The BiFeO3 film with 5 M doped La was prepared with sol–gel and ZrO2 film was physically deposited with rf sputtering. Films structural characteristics were obtained using X-ray diffraction and scanning electron microscopy (SEM). The ferroelectric film shows the perovskite structure with orientation (110)/(104) when annealed in the range from 400 to 700 °C. The dielectric film shows an amorphous structure for the same range of annealing temperature. Electrical and ferroelectric properties were obtained by fabricating and characterizing metal/ferroelectric/silicon (MFS), metal/ferroelectric/metal (MFM), metal/insulator/silicon (MIS), metal/ferroelectric/insulator/metal (MFIM) and metal/ferroelectric/insulator/silicon (MFIS) capacitor structures with ferroelectric film of 200 nm thickness and dielectric film of various thicknesses. MFS structure shows a maximum memory window of 3.5 V and leakage current density of 1.4 × 10–8 A/cm2 with ferroelectric film annealed at 500 °C. The memory window was further improved to 6.62 V and leakage current to the order 10–10 A/cm2 with the introduction of 9 nm insulator layer between ferroelectric and silicon. The same device shows an excellent endurance property tested for 1012 cycles and data retention tested for 5.56 h. The device shows a breakdown of 43 V, which is 9 V higher than the MFS structure. To the best of author’s knowledge, this is the first report to integrate La-doped BiFeO3 on ZrO2 (high-k) dielectric for non-volatile memory applications.

Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs

The gate induced drain leakage (GIDL) effect in negative capacitance (NC) FinFET is investigated. A Landau–Ginzburg–Devonshire equation (which considers the polarization gradient in ferroelectric material) is used to estimate the characteristics of the NC FinFET. Specifically, metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NC FinFETs are compared, in order to figure out the effect of the internal metal layer on the GIDL effect. To analyze the impact of the polarization gradient on the GIDL effect in NC FinFET, a polarization gradient coefficient is varied. For MFMIS, the polarization gradient doesn't significantly affect the device performance. The subthreshold swing improves but the GIDL effect deteriorates because of the “uniform” NC effect in channel region. For MFIS, the device performance is explicitly affected by the polarization gradient. Smaller polarization gradients result in non-uniform NC effect in channel region, resulting in severe GIDL effects. On the other hand, higher polarization gradients alleviate GIDL effects.

Sustained Benefits of NCFETs Under Extreme Scaling to the End of the IRDS

We use full quantum-transport simulations by coupling the Landau-Khalatnikov (LK) and Poisson equations self-consistently with the nonequilibrium Green's function (NEGF) formalism, and calibrated to experimental results, to investigate extremely scaled negative-capacitance, field-effect transistors (NCFETs) having dimensions toward the end of the international roadmap for devices and systems (IRDS), that is, to sub-10-nm gate lengths, where channel transport can be expected to be governed by quantum-mechanical effects. We identify how the ferroelectric affects both thermionic emission and quantum-mechanical tunneling of electrons, both of which are relevant transport mechanisms for these ultrascaled devices. Our detailed results show that while NCFETs are not immune to the increase in the tunneling as they undergo extreme channel-length scaling, the metal-ferroelectric-insulator-semiconductor (MFIS) structure will continue to offer benefits to a subthreshold slope, ON- and OFF-currents, drain-induced barrier lowering, and output conductance until the end of the roadmap. These improvements allow MFIS NCFETs of any given node to achieve similar performance to nonferroelectric devices of the immediately preceding (higher-dimension) node. The fundamental reason for the improvements is identified to be the presence of voltage amplification at the top of the barrier (TOB) and suppression of TOB movement with drain voltage.

Limits on Hysteresis-Free Sub-60 mV/Decade Operation of MFIS Nanowire Transistor

In this work, we present purely device-dependent conditions for achieving hysteresis-free sub-60 mV/decade (HF-sub-60) current transition in metal-ferroelectric-insulator-semiconductor (MFIS) nanowire transistor. The proposed bias-independent conditions for HF-sub-60 operation are also verified through conventional bias-dependent capacitance matching. Optimal ranges of ${T} _{\text {fe}}$ for achieving HF-sub-60 current transition are examined for 1) varying radii of nanowire; 2) three ferroelectric materials (Al-HfO2, hafnium zirconium oxide (HZO) and Y-HfO2); 3) nanowire and planar architectures; and 4) coercive field and remnant polarization variations. Furthermore, the impact of gate length scaling is incorporated into the developed model. The proposed methodology in this article provides new and detailed guidelines into the selection of device and process parameters, ferroelectric materials, and device topologies for facilitating high internal voltage amplification factor, improved subthreshold swing and hysteresis-free operation in MFIS transistors.

Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations

The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator–semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NC-FDSOI model is computationally efficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators.

Effect of depolarization field on steep switching characteristics in negative capacitance field effect transistors

A theoretical model for describing the effect of depolarization field (Ed) in the negative capacitance (NC) field effect transistor (FET) was derived. Based on this model, the electrical properties of the metal-ferroelectric-insulator-semiconductor (MFIS) field effect transistor including the relationship between the depolarizing field and the gate voltage (Vg), Ed and silicon surface potential, and the drain-source current of NC-FET and Vg (transfer characteristics) were theoretically investigated. The computing results demonstrated that the surface potential amplification and the steep subthreshold slope characteristics happened at the gate voltage of about 0.4 V, results from the steep increase of Ed dependent on Vg in the NC-FETs. It is expected that the derived results may provide some insight into the design and performance improvement for the NC-MFIS-FET.

RF Performance Projections of Negative-Capacitance FETs: fT , f max, and gmfT/ID

As continuous development and optimization of negative-capacitance field-effect transistors (NCFETs) are pursued for digital applications, it is also desirable to examine the radio frequency (RF) performance of these devices, especially devices with the metal-ferroelectric- insulator-semiconductor (MFIS) structure. In this article, we use a combination of physics-based modeling and small-signal circuits to investigate the RF performance of MFIS NCFETs using three key device figures of merit: the well-known unity-current-gain (cutoff) frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and the well-known maximum oscillation frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> , and another important metric specified by g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> , where g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> is the transconductance and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> is the dc drain current. We find that MFIS NCFETs achieve similar f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> performance to conventional MOSFETs, but offer a significant advantage in g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> .

A Junctionless Accumulation Mode NC-FinFET Gate Underlap Design for Improved Stability and Self-Heating Reduction

A novel metal ferroelectric insulator semiconductor (MFIS) -type junctionless accumulation mode (JAM) negative capacitance (NC)-FinFET with reduced self-heating is proposed for the low-power Internet-of-Things (IoT) applications at 7-nm technology node. Using 3-D TCAD simulations, we have varied the gate to source/drain junction overlap length, which shows that increased junction overlap offers reduced gate-induced drain leakage (GIDL) in NC-FinFET. We then show that the proposed JAM NC-FinFET provides superior ON -state current ( ${I}_{\text{ON}}$ ) to OFF -state current ( ${I}_{\text{OFF}}$ ) ratio with and without the self-heating effect (SHE). It also gives stable peak transconductance ( ${g}_{\text {m}}$ ) with and without SHE consideration due to reduced lattice temperature ( ${T}_{\text {I}} = 321$ K). A better capacitance matching due to the presence of depletion capacitance ( ${C}_{\text {dep}}$ ) is also observed, thereby resulting in low-hysteresis NC-FinFET design. The impact of gate metal work function variation on the hysteresis behavior of NC and JAM-NC-FinFET is also reported in this article. Furthermore, we show that the proposed JAM-NC-FinFET offers superior transconductance generation factor (TGF) in comparison with conventional NC-FinFET in the subthreshold region, making it a potential candidate for low-power applications.

Gate-Induced Drain Leakage in Negative Capacitance FinFETs

In this article, we analyze the issue of gate-induced-drain-leakage (GIDL) in metal-ferroelectric-insulator-semiconductor (MFIS)-type negative capacitance fin field-effect transistor (NC-FinFET) using 3-D technology computer-aided design (TCAD) simulations. We present a comprehensive analysis of GIDL characteristics on 7-nm technology node with respect to the variation of ferroelectric and silicon body thicknesses, source/drain junction placement, and source/drain doping concentration of NC-FinFET. We find that in NCFET, steeper energy band profiles near the source and drain side caused by fringing field coupling to the ferroelectric result in a prior and larger onset of the longitudinal band to band tunneling (L-BTBT) current compared to the baseline FinFET. Also, we find that, unlike the conventional FinFET, NC-FinFET shows the nonmonotonic trend in the occurrence of the L-BTBT component as we scale down the channel length of the device due to the reverse short channel effect.

Improvement in Long-Term and High-Temperature Retention Stability of Ferroelectric Field-Effect Memory Transistors With Metal–Ferroelectric–Metal–Insulator–Semiconductor Gate-Stacks Using Al-Doped HfO2 Thin Films

Nonvolatile memory characteristics of the ferroelectric field-effect transistors (FeFETs) were investigated by introducing the metal–ferroelectric–metal–insulator–semiconductor (MFMIS) gate-stacks, employing Al-doped HfO2 (Al:HfO2) ferroelectric thin films. The obtained memory window (MW) of the MFMIS FETs increased from 1.0 to 2.8 V by increasing the areal ratios of the metal–insulator–semiconductor (MIS) to the metal–ferroelectric–metal (MFM) (SI/SF) from 8 to 32. The device with an SI/SF ratio of 16 exhibited a 3-order-of-magnitude on/off memory margin even with a program pulse duration of 500 ns. The long-term data retention was also verified by improving the tolerance against the depolarization field by introducing the MFMIS gate-stacks, which can use fully saturated polarization. The temperature-dependent memory performance and operational reliabilities of the MFMIS-FETs were also investigated at high temperatures to exploit fully the thermal stability of the Al:HfO2. The obtained MWs were not markedly degraded for a retention time of 104 s from room temperature (RT) to 80 °C.

Impact of Radiation Effect on Ferroelectric Al-Doped HfO2 Metal-Ferroelectric- Insulator-Semiconductor Structure

The $\gamma $ -ray total dose radiation effects on ferroelectric Al-doped HfO2 (HfAlO) thin films with an n-type Si substrate were studied. The $I$ - $V$ , $P$ - $V$ , $C$ - $V$ and fatigue characteristics of the HfAlO-based Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure were analyzed with the increasing total dose from 0 to 1 Mrad (Si). The remnant polarization ( $P_{\mathrm {r}}$ ) values, the capacitance ( $C$ ) values and the switching voltage ( $V_{\mathrm {c}}$ ) of this MFIS gate structure decreased with the increasing total dose. A TCAD model of Metal/HfAlO/SiO2/Si (MFIS) was proposed to explain the degradation mechanism of ferroelectric properties of the MFIS structure. We find that the new interface defects caused by radiation can reduce the electric field strength with the increasing total dose, which can significantly influence the irradiation properties of the HfAlO/SiO2/n-Si gate structure. These results provide the basis to applications for the HfO2-based devices in radiation working environment.

Improvements in the synaptic operations of ferroelectric field-effect transistors using Hf0.5Zr0.5O2 thin films controlled by oxygen partial pressures during the sputtering deposition process

Synaptic operations of metal–ferroelectric–metal–insulator–semiconductor (MFMIS) field-effect transistors using HfxZr1−xO2 thin films were successfully demonstrated and optimized by controlling oxygen partial pressure during sputtering deposition.