Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations

Abstract

The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator–semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NC-FDSOI model is computationally efficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators.